DG2016DQ-T1-E3 データシートの表示（PDF） - Vishay Semiconductors
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DG2016DQ-T1-E3 Datasheet PDF : 8 Pages
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DG2016, DG2026
Vishay Siliconix
TEST CIRCUITS
V+
V+
NO
VNO
COM
NC
VNC
IN
GND
RL
50
VO
CL
35 pF
Logic VINH
Input
VINL
VNC = VNO
VO
Switch 0 V
Output
90 %
tD
tr < 5 ns
tf < 5 ns
tD
CL (includes fixture and stray capacitance)
Figure 2. Break-Before-Make Interval
V+
Vgen
Rgen
+
VIN = 0 - V+
V+
NC or NO
IN
GND
COM
VOUT
VOUT
VOUT
CL = 1 nF
IN
On
Off
On
Q = VOUT x CL
IN depends on switch configuration: input polarity
determined by sense of switch.
Figure 3. Charge Injection
V+
10 nF
V+
NC or NO
IN
COM COM
RL
GND
Analyzer
VCOM
Off Isolation = 20 log VNO/ NC
Figure 4. Off-Isolation
0 V, 2.4 V
V+
10 nF
V+
COM
IN
0 V, 2.4 V
NC or NO
GND
Meter
HP4192A
Impedance
Analyzer
or Equivalent
f = 1 MHz
Figure 5. Channel Off/On Capacitance
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72030.
www.vishay.com
Document Number: 72030
6
S11-1185-Rev. D, 13-Jun-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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