DS21Q50LN データシートの表示（PDF） - Maxim Integrated

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DS21Q50LN

Quad E1 Transceiver

Maxim Integrated 

2. PIN DESCRIPTION

DS21Q50

Table 2-1. Pin Assignments (by Function)

NAME

PIN

PARALLEL PORT SERIAL PORT TYPE

ENABLED

ENABLED

FUNCTION

[Serial Port Mode in Brackets]

71

4/8/16MCK

O

4.096MHz, 8.192MHz, or 16.384 MHz

Clock

45

A0

ICES

I

Address Bus Bit 0/Serial Port

[Input Clock Edge Select]

46

A1

OCES

I

Address Bus Bit 1/Serial Port

[Output Clock Edge Select]

47

A2

I Address Bus Bit 2

48

A3

I Address Bus Bit 3

49

A4

I Address Bus Bit 4

70

AJACKI

I Alternate Jitter Attenuator Clock Input

69

AJACKO

O Alternate Jitter Attenuator Clock Output

50

ALE(AS)/A5

I Address Latch Enable/Address Bus Bit 5

96

BTS0

Bus Type Select 0

97

BTS1

Bus Type Select 1

98

CS

I Chip Select

19

D0/AD0

I/O Data Bus Bit0/Address/Data Bus Bit 0

20

D1/AD1

I/O Data Bus Bit1/Address/Data Bus Bit 1

21

D2/AD2

I/O Data Bus Bit 2/Address/Data Bus Bit2

22

D3/AD3

I/O Data Bus Bit 3/Address/Data Bus Bit 3

23

D4/AD4

I/O Data Bus Bit4/Address/Data Bus Bit 4

24

D5/AD5

I/O Data Bus Bit 5/Address/Data Bus Bit 5

25

D6/AD6

I/O Data Bus Bit 6/Address/Data Bus Bit 6

44

D7/AD7

SDO

I/O

Data Bus Bit 7/Address/Data Bus Bit 7

[Serial Data Output]

84

DVDD1

— Digital Positive Supply

59

DVDD2

— Digital Positive Supply

34

DVDD3

— Digital Positive Supply

9

DVDD4

— Digital Positive Supply

83

DVSS1

— Digital Signal Ground

58

DVSS2

— Digital Signal Ground

33

DVSS3

— Digital Signal Ground

8

DVSS4

— Digital Signal Ground

—

EQVSS1

— Equalizer Analog Signal Ground

—

EQVSS2

— Equalizer Analog Signal Ground

—

EQVSS3

— Equalizer Analog Signal Ground

—

EQVSS4

94

INT

— Equalizer Analog Signal Ground

O Interrupt

73

MCLK

I Master Clock Input

61

OUTA1

O User Selectable Output A

36

OUTA2

O User Selectable Output A

11

OUTA3

O User Selectable Output A

86

OUTA4

O User Selectable Output A

9 of 87

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