DS21Q58 データシートの表示（PDF） - Maxim Integrated

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DS21Q58

E1 Quad Transceiver

Maxim Integrated 

DS21Q58 E1 Quad Transceiver

3. BLOCK DIAGRAM

Figure 3-1. Block Diagram

MCLK

RECEIVE

SIDE

RRING1

RTIP1

VCO/PLL

USER OUTPUT

SELECT

DATA

CLOCK

SYNC

RECEIVE-SIDE

FRAMER

ELASTIC

STORE AND

IBO BUFFER

OUTA1

OUTB1

RSER1

SYSCLK1

RSYNC1

TRANSMIT

SIDE

TRING1

TTIP1

Dallas

Semiconductor

DS21Q58

TRANSCEIVER 1 OF 4

PARALLEL AND TEST CONTROL PORT

(ROUTED TO ALL BLOCKS)

SYNC

CONTROL

DATA

CLOCK

SYNC

TRANSMIT-

SIDE

FORMATTER

IBO

BUFFER

DIVIDE-

BY-2/4/8

A

BU Ck

MUX

B

C

TRANSMIT

CLOCK SOURCE

A

Tx Ck

MUX B

LOTC

DETECT

TSYNC1

TSER1

TCLK1

BACKUP CLOCK MUX

TRANSCEIVERS 2, 3, 4

RCLK TRANSCEIVER 2

RCLK TRANSCEIVER 3

RCLK TRANSCEIVER 4

SYSTEM CLOCK

INTERFACE

MUX

ALTERNATE

JITTER

ATTENUATOR

4/8/16MHz

SYNTHESIZER

REFCLK

4/8/16MCK

7 of 74

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