DS2726 データシートの表示（PDF） - Maxim Integrated

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DS2726

5-Cell to 10-Cell Li+ Protector with Cell Balancing

Maxim Integrated 

5-Cell to 10-Cell Li+ Protector with

Cell Balancing

Li+ Protection Conditions

Overvoltage, OV. If any cell voltage (VCELL) exceeds

the overvoltage threshold, VOV, for a period longer than

overvoltage delay, tOVD, the DS2726 shuts off the

external charge FET. When VCELL falls below the

charge-enable threshold VCE, the DS2726 turns the

charge FET on. The discharge FET remains enabled

during the overvoltage event. Care should be taken

while discharging during an OV condition because the

current drawn by the load is going through the body

diode of the CC FET.

Undervoltage, UV. If VCELL drops below the undervolt-

age threshold, VUV, for a period longer than undervolt-

age delay, tUVD, the DS2726 shuts off the charge and

discharge FETs and enters Sleep Mode. The device

remains in Sleep Mode until a charger is detected, at

which point the DS2726 wakes up and enables the CC

FET. The DC FET remains disabled until every cell is

above the VUV_REL threshold. Care should be taken

while charging during a UV event because the charge

current is flowing through the body diode of the DC FET.

Discharge Overcurrent, DOC. If VSNS is less than

VRDOC for a period longer than tDOCD, the DS2726

shuts off the external discharge FET. The discharge

current path is not reestablished until VPKP rises above

VVIN - VTP. The DS2726 provides a test current of value

ITST from the PKP pin to the VIN pin to detect the

removal of the offending low-impedance load. ITST is

not disabled if an undervoltage condition is reached.

Short Circuit, SC. If VSNS is less than VRSC for a peri-

od longer than short-circuit delay tSCD, the DS2726

shuts off the external discharge FET. The discharge

current path is not reestablished until VPKP rises above

VVIN - VTP. The DS2726 provides a test current of value

ITST from the PKP pin to the VIN pin to detect the

removal of the short. ITST is disabled if an undervoltage

condition is reached.

Summary. All the protection conditions described are

logic ORed to affect the CC and DC outputs:

DC = (Undervoltage) or (Discharge Overcurrent) or

(Short Circuit)

CC = (Overvoltage) or (Undervoltage and Charger

Detect)

VCELL

CHARGE

VSNS

DISCHARGE

CC

tOVD

tOVD

DC

tSCD

tOCD

POWER

MODE

Figure 3. Li+ Protection Circuitry Example Waveforms

VOV

VCE

VUV_REL

VUV

VVIN

VRDOC

VRSC

VOHCC

tUVD

VOLCC

VOHDC

tUVD

VOLDC

ACTIVE

SLEEP

10 ______________________________________________________________________________________

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