DSP56011 データシートの表示（PDF） - Motorola => Freescale
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DSP56011 Datasheet PDF : 82 Pages
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Specifications
RESET, Stop, Mode Select, and Interrupt Timing
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (Continued)
All Frequencies
No.
Characteristics
Unit
PRELIMINARY Min
Max
22 Delay from General Purpose Output valid to interrupt
request deassertion for level sensitive fast interrupts—
if second interrupt instruction is:2
• Single cycle
• Two cycles
TL – 31
ns
(2 × TC) + TL – ns
31
25 Duration of IRQA assertion for recovery from stop
12
state
—
ns
27 Duration for level-sensitive IRQA assertion to ensure
interrupt service (when exiting Stop mode)
• Stable external clock, OMR Bit 6 = 1
• Stable external clock, PCTL Bit 17 = 1
6 × TC+ TL
—
ns
12
—
ns
Notes: 1. This timing requirement is sensitive to the quality of the external PLL capacitor connected to the
PCAP pin. For capacitor values less than or equal to 2 nF, asserting RESET according to this timing
requirement will ensure proper processor initialization for capacitors with a delta C/C less than
0.5%. (This is typical for ceramic capacitors.) For capacitor values greater than 2 nF, asserting
RESET according to this timing requirement will ensure proper processor initialization for
capacitors with a delta C/C less than 0.01%. (This is typical for Teflon, polystyrene, and
polypropylene capacitors.) However, capacitors with values greater than 2 nF with a delta C/C
greater than 0.01% may require longer RESET assertion to ensure proper initialization.
2. When using fast interrupts and IRQA and IRQB are defined as level-sensitive, timing 22 applies to
prevent multiple interrupt service. To avoid these timing restrictions, negative-edge-triggered
configuration is recommended when using fast interrupts. Long interrupts are recommended
when using level-sensitive configuration.
RESET
10
Figure 2-2 Reset Timing
VIHR
AA0251
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-7
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