DSP56300 データシートの表示（PDF） - Freescale Semiconductor
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DSP56300 Datasheet PDF : 108 Pages
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Specifications
2.5.4 Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6
No.
Characteristics
Expression
8 Delay from RESET assertion to all pins at reset value3
9 Required RESET duration4
• Power on, external clock generator, PLL disabled
• Power on, external clock generator, PLL enabled
• Power on, internal oscillator
• During STOP, XTAL disabled (PCTL Bit 16 = 0)
• During STOP, XTAL enabled (PCTL Bit 16 = 1)
• During normal operation
10 Delay from asynchronous RESET deassertion to first external address
output (internal reset deassertion)5
• Minimum
• Maximum
11 Synchronous reset set-up time from RESET deassertion to CLKOUT
Transition 1
• Minimum
• Maximum
12 Synchronous reset deasserted, delay time from the CLKOUT Transition
1 to the first external address output
• Minimum
• Maximum
13 Mode select setup time
14 Mode select hold time
15 Minimum edge-triggered interrupt request assertion width
16 Minimum edge-triggered interrupt request deassertion width
17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external
memory access address out valid
• Caused by first interrupt instruction fetch
• Caused by first interrupt instruction execution
18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-
purpose transfer output valid caused by first interrupt instruction
execution
19 Delay from address output valid caused by first interrupt instruction
execute to interrupt request deassertion for level sensitive fast
interrupts1, 7, 8
20 Delay from RD assertion to interrupt request deassertion for level
sensitive fast interrupts1, 7, 8
21 Delay from WR assertion to interrupt request deassertion for level
sensitive fast interrupts1, 7, 8
• DRAM for all WS
• SRAM WS = 1
• SRAM WS = 2, 3
• SRAM WS ≥ 4
22 Synchronous interrupt set-up time from IRQA, IRQB, IRQC, IRQD, NMI
assertion to the CLKOUT Transition 2
23 Synchronous interrupt delay time from the CLKOUT Transition 2 to the
first external address output valid caused by the first instruction fetch
after coming out of Wait Processing state
• Minimum
• Maximum
—
50 × ETC
1000 × ETC
75000 × ETC
75000 × ETC
2.5 × TC
2.5 × TC
3.25 × TC + 2.0
20.25 × TC + 10
TC
3.25 × TC + 1.0
20.25 × TC + 1.0
4.25 × TC + 2.0
7.25 × TC + 2.0
10 × TC + 5.0
(WS + 3.75) × TC – 10.94
(WS + 3.25) × TC – 10.94
(WS + 3.5) × TC – 10.94
(WS + 3.5) × TC – 10.94
(WS + 3) × TC – 10.94
(WS + 2.5) × TC – 10.94
8.25 × TC + 1.0
24.75 × TC + 5.0
100 MHz
Min Max
—
26.0
Unit
ns
500.0
—
ns
10.0
—
µs
0.75
—
ms
0.75
—
ms
25.0
—
ns
25.0
—
ns
34.5
—
ns
—
212.5 ns
5.9
—
ns
—
10.0
ns
33.5
—
ns
—
203.5 ns
30.0
—
ns
0.0
—
ns
6.6
—
ns
6.6
—
ns
44.5
—
ns
74.5
—
ns
105.0
—
ns
—
Note 8 ns
—
Note 8 ns
—
Note 8 ns
—
Note 8 ns
—
Note 8 ns
—
Note 8 ns
5.9
TC
ns
83.5
—
ns
—
252.5 ns
DSP56309 Technical Data, Rev. 7
2-6
Freescale Semiconductor
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