DSPIC33FJ32GP202(2007) データシートの表示（PDF） - Microchip Technology

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DSPIC33FJ32GP202
(Rev.:2007)

High-Performance, 16-Bit Microcontrollers

Microchip Technology 

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

2.0 CPU

Note:

This data sheet summarizes the features

of the dsPIC33FJ32GP202/204 and

dsPIC33FJ16GP304 devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC33F

Family Reference Manual”.

The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

CPU module has a 16-bit (data) modified Harvard archi-

tecture with an enhanced instruction set, including signifi-

cant support for DSP. The CPU has a 24-bit instruction

word with a variable length opcode field. The Program

Counter (PC) is 23 bits wide and addresses up to 4M x 24

bits of user program memory space. The actual amount of

program memory implemented varies by device. A sin-

gle-cycle instruction prefetch mechanism is used to help

maintain throughput and provides predictable execution.

All instructions execute in a single cycle, with the excep-

tion of instructions that change the program flow, the dou-

ble word move (MOV.D) instruction and the table

instructions. Overhead-free program loop constructs are

supported using the DO and REPEAT instructions, both of

which are interruptible at any point.

The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

devices have sixteen, 16-bit working registers in the pro-

grammer’s model. Each of the working registers can serve

as a data, address or address offset register. The 16th

working register (W15) operates as a software Stack

Pointer (SP) for interrupts and calls.

The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

instruction set has two classes of instructions: MCU and

DSP. These two instruction classes are seamlessly inte-

grated into a single CPU. The instruction set includes

many addressing modes and is designed for optimum C

compiler efficiency. For most instructions, the

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 is

capable of executing a data (or program data) memory

read, a working register (data) read, a data memory write

and a program (instruction) memory read per instruction

cycle. As a result, three parameter instructions can be

supported, allowing A + B = C operations to be executed

in a single cycle.

A block diagram of the CPU is shown in Figure 2-1. The

programmer’s model for the dsPIC33FJ32GP202/204 and

dsPIC33FJ16GP304 is shown in Figure 2-2.

2.1 Data Addressing Overview

The data space can be addressed as 32K words or

64 Kbytes and is split into two blocks, referred to as X and

Y data memory. Each memory block has its own

independent Address Generation Unit (AGU). The MCU

class of instructions operates solely through the X mem-

ory AGU, which accesses the entire memory map as one

linear data space. Certain DSP instructions operate

through the X and Y AGUs to support dual operand reads,

which splits the data address space into two parts. The X

and Y data space boundary is device-specific.

Overhead-free circular buffers (Modulo Addressing mode)

are supported in both X and Y address spaces. The

Modulo Addressing removes the software boundary

checking overhead for DSP algorithms. Furthermore, the

X AGU circular addressing can be used with any of the

MCU class of instructions. The X AGU also supports

Bit-Reversed Addressing to greatly simplify input or output

data reordering for radix-2 FFT algorithms.

The upper 32 Kbytes of the data space memory map can

optionally be mapped into program space at any 16K

program word boundary defined by the 8-bit Program

Space Visibility Page (PSVPAG) register. The program to

data space mapping feature lets any instruction access

program space as if it were data space.

2.2 DSP Engine Overview

The DSP engine features a high-speed 17-bit by 17-bit

multiplier, a 40-bit ALU, two 40-bit saturating

accumulators and a 40-bit bidirectional barrel shifter. The

barrel shifter is capable of shifting a 40-bit value up to 16

bits right or left, in a single cycle. The DSP instructions

operate seamlessly with all other instructions and have

been designed for optimal real-time performance. The

MAC instruction and other associated instructions can

concurrently fetch two data operands from memory while

multiplying two W registers and accumulating and

optionally saturating the result in the same cycle. This

instruction functionality requires that the RAM data space

be split for these instructions and linear for all others. Data

space partitioning is achieved in a transparent and flexible

manner through dedicating certain working registers to

each address space.

2.3 Special MCU Features

The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

features a 17-bit by 17-bit single-cycle multiplier that is

shared by both the MCU ALU and DSP engine. The mul-

tiplier can perform signed, unsigned and mixed-sign mul-

tiplication. Using a 17-bit by 17-bit multiplier for 16-bit by

16-bit multiplication not only allows you to perform

mixed-sign multiplication, it also achieves accurate results

for special operations, such as (-1.0) x (-1.0).

The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

supports 16/16 and 32/16 divide operations, both frac-

tional and integer. All divide instructions are iterative oper-

ations. They must be executed within a REPEAT loop,

resulting in a total execution time of 19 instruction cycles.

The divide operation can be interrupted during any of

those 19 cycles without loss of data.

A 40-bit barrel shifter is used to perform up to a 16-bit left

or right shift in a single cycle. The barrel shifter can be

used by both MCU and DSP instructions.

© 2007 Microchip Technology Inc.

Preliminary

DS70290A-page 13

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