EM78P157N データシートの表示（PDF） - ELAN Microelectronics

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EM78P157N

8-Bit Microcontroller with OTP ROM

ELAN Microelectronics 

EM78P157N

8-Bit Microcontroller with OTP ROM

4.1.1 Indirect Addressing (R0) Register

R0 is not a physically implemented register. Its major function is to perform as an

indirect addressing pointer. Any instruction using R0 as a pointer actually accesses

data pointed by the RAM Select Register (R4).

4.1.2 Time Clock / Counter (R1) Register

„ Increased by an external signal edge, which is defined by TE bit (CONT-4) through

the TCC pin, or by the instruction cycle clock.

„ Writable and readable as any other registers.

„ Defined by resetting PAB (CONT-3).

„ The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.

„ The contents of the prescaler counter will be cleared only when TCC register is

written with a value.

4.1.3 Program Counter and Stack (R2) Register

„ Depending on the device type, R2 and hardware stack are 10-bits wide. The R2

structure is depicted in Fig. 4-2 below.

„ Generates 1024×13 bits on-chip OTP ROM addresses to the relative programming

instruction codes. One program page is 1024 words long.

„ R2 is set as all “0” when under RESET condition.

„ "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,

"JMP" allows PC to go to any location within a page.

„ "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into

the stack. Thus, the subroutine entry address can be located anywhere within a

page.

„ "RET" ("RETL k," "RETI") instruction loads the program counter with the contents

of the top-level stack.

„ "ADD R2, A" allows the contents of ‘A’ to be added to the current PC, and the ninth

and tenth bits of the PC are cleared.

„ "MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of

the PC, and the ninth and tenth bits of the PC are cleared.

„ Any instruction that writes to R2 (e.g., "ADD R2,A," "MOV R2,A," "BC R2,6",⋅etc.)

will cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the

computed jump is limited to the first 256 locations of a page.

„ All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction

that would change the contents of R2. Such instruction will need one more

instruction cycle.

6•

Product Specification (V1.0) 09.22.2005

(This specification is subject to change without further notice)

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