EP7212-CV データシートの表示（PDF） - Cirrus Logic

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EP7212-CV

High-Performance, Low-Power System-on-Chip with LCD Controller and Digital Audio Interface (DAI)

Cirrus Logic 

EP7212

Table 19. Effect of Endianness on Read Operations .................................................................... 37

Table 20. Effect of Endianness on Write Operations .................................................................... 37

Table 21. Serial Interface Options................................................................................................. 39

Table 22. Serial-Pin Assignments ................................................................................................. 39

Table 23. ADC Interface Operation Frequencies .......................................................................... 43

Table 24. Instructions Supported in JTAG Mode .......................................................................... 50

Table 25. Device ID Register ........................................................................................................ 51

Table 26. EP7212 Memory Map in External Boot Mode ............................................................... 53

Table 27. EP7212 Internal Registers (Little Endian Mode) ........................................................... 55

Table 28. EP7212 Internal Registers (Big Endian Mode).............................................................. 57

Table 29. SYSCON1 ..................................................................................................................... 59

Table 30. SYSCON2 ..................................................................................................................... 61

Table 31. SYSCON3 ..................................................................................................................... 63

Table 32. SYSFLG ........................................................................................................................ 64

Table 33. SYSFLG2 ...................................................................................................................... 66

Table 34. INTSR1.......................................................................................................................... 67

Table 35. INSTR2.......................................................................................................................... 69

Table 36. INTSR3.......................................................................................................................... 70

Table 37. Values of the Bus Width Field ....................................................................................... 72

Table 38. Values of the Wait State Field at 13 MHz and 18 MHz ................................................. 72

Table 39. Values of the Wait State Field at 36 MHz...................................................................... 72

Table 40. MEMCFG ...................................................................................................................... 73

Table 41. LED Flash Rates ........................................................................................................... 75

Table 42. LED Duty Ratio.............................................................................................................. 75

Table 43. PMPCON....................................................................................................................... 76

Table 44. Sense of PWM control lines .......................................................................................... 76

Table 45. UARTDR1-2 UART1-2 .................................................................................................. 77

Table 46. UBRLCR1-2 UART1-2 .................................................................................................. 78

Table 47. LCDCON ....................................................................................................................... 79

Table 48. Grayscale Value to Color Mapping................................................................................ 81

Table 49. SYNCIO......................................................................................................................... 82

Table 50. DAI Control Register ..................................................................................................... 86

Table 51. DAI Data Register 0 ...................................................................................................... 89

Table 52. DAI Data Register 1 ...................................................................................................... 90

Table 53. DAI Data Register 2 ...................................................................................................... 91

Table 54. DAI Control, Data and Status Register Locations ......................................................... 92

Table 55. absolute Maximum Ratings ........................................................................................... 96

Table 56. Recommended Operating Conditions ........................................................................... 96

Table 57. DC Characteristics ........................................................................................................ 96

Table 58. AC Timing Characteristics............................................................................................. 98

Table 59. Timing Characteristics................................................................................................... 99

Table 60. I/O Buffer Output Characteristics ................................................................................ 111

Table 61. 208-Pin LQFP Numeric Pin Listing.............................................................................. 111

Table 62. EP7212 Hardware Test Modes ................................................................................... 114

Table 63. Oscillator and PLL Test Mode Signals ........................................................................ 115

Table 64. Software Selectable Test Functionality ....................................................................... 115

Table 65. 208-Pin LQFP Numeric Pin Listing.............................................................................. 117

Table 66. 256-Ball PBGA Ball Listing.......................................................................................... 121

10

DS474PP1

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