ESDA25LY(2010) データシートの表示（PDF） - STMicroelectronics
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ESDA25LY Datasheet PDF : 10 Pages
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Calculation of the clamping voltage
2
Calculation of the clamping voltage
ESDA25LY
2.1
Use of the dynamic resistance
The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB
designers need to calculate easily the clamping voltage VCL. This is why we give the
dynamic resistance in addition to the classical parameters. The voltage across the
protection cell can be calculated with the following formula:
VCL = VBR + Rd IPP
Where Ipp is the peak current through the ESDA cell.
3
Dynamic resistance measurement
The short duration of the ESD has led us to prefer a more adapted test wave, as below
defined, to the classical 8/20 µs and 10/1000 µs surges.
As the value of the dynamic resistance remains stable for a surge duration lower than 20 µs,
the 2.5 µs rectangular surge is well adapted. In addition both rise and fall times are
optimized to avoid any parasitic phenomenon during the measurement of Rd.
Figure 9. 2.5 µs duration measurement wave
I
IPP
t
2µs
tp = 2.5µs
4/10
Doc ID 16914 Rev 1
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