ML2264CCP データシートの表示（PDF） - Micro Linear Corporation

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ML2264CCP

4-Channel High-Speed 8-Bit A/D Converter with T/H (S/H)

Micro Linear Corporation 

1.0 FUNCTIONAL DESCRIPTION

The ML2264 uses a two stage flash technique for A/D

conversion. This technique first performs a 4 bit flash

conversion on VIN to determine the 4 MSB’s. These 4

MSB’s are then cycled through an internal DAC to

recreate the analog input. This reconstructed analog input

signal from the DAC is then subtracted from the input, and

the difference voltage is converted by a second 4 bit flash

conversion, providing the 4 LSB’s of the output data word.

1.1 MULTIPLEXER ADDRESSING

The ML2264 contains a 4-channel single ended analog

multiplexer. A particular input channel is selected by using

the address inputs A0 and A1. The relationship between

the address inputs, A0 and A1, and the analog input

selected is shown in Table 1.

Selected

Analog Channel

A IN 1

A IN 2

A IN 3

A IN 4

Address Input

A0

A1

0

0

1

0

0

1

1

1

Table 1. Multiplexer Address Decoding

The address inputs are latched into the ML2264 on the

falling edge of the RD, WR, or CS depending on the state

of pins SH/TH and mode as shown in Table 2.

Address Latching

Signal

RDØ

WRØ

CSØ

CSØ

Mode

GND

VCC

GND

VCC

Operation Mode

GND

GND

VCC

VCC

Table 2.

In the Sample & Hold mode of operation CS is used as the

address latch enable, allowing for continuous conversions

without addressing a given analog input for each

conversion.

The Track & Hold mode of operation requires an analog

input to be addressed and latched for each conversion

that the ML2264 performs.

1.2 ANALOG INPUTS

The analog input on the ML2264 behaves differently than

inputs on conventional converters. The analog input

current requirements change while the conversion is in

progress, and the amount of input current depends on

what cycle the converter is in.

ML2264

The equivalent input circuit for the converter is shown in

Figure 8. When the conversion starts in the T/H mode

(WRØ in the WR-RD mode or RDØ in the RD mode) S1,

S4 and S6 close and S3 opens. This period is known as the

acquisition period where the MSB flash converter tracks

the input signal and the LSB flash converter samples it.

During this period, VIN is connected to the 16 MSB and

15 LSB comparators. Thus 38pF of input capacitance must

be charged up through the combined RON resistance of

the internal analog switches plus any external source

resistance, RS. In addition, there is a stray capacitance of

approximately 11pF that needs to be charged through the

external source resistance RS. This period ends in the WR-

RD mode when WR or by an internal timer in the RD

mode. At this point S1 and S4 open and the analog input

at VIN is no longer being sampled; thus during this time

the analog voltage on VIN does not affect converter

performance.

As shown above, the critical period for charging up the

analog input occurs when the MSB and LSB comparators

are sampling the input, known as the acquisition period.

The source of the external signal on VIN must adequately

charge up the analog voltage during the acquisition

period. To do this, the input must settle within the

required analog accuracy tolerance at least 50ns before

the end of the acquisition period so that the MSB

comparators have adequate time to make the correct

decision. If more time is needed due to finite charging or

settling time of the external source, the WR low period

can be extended in WR-RD mode. In RD mode, since the

acquisition time is fixed by internal delays, the burden is

on the external source to charge up and settle the input

adequately.

When the ML2264 operates in the S/H mode (pin 23 =

VCC) both the MSB and the LSB flash converter perform a

true sample and hold operation during the acquisition or

sampling period. This period starts after the falling edge of

INT and ends with the falling edge of WR in the WR-RD

mode or the falling edge of RD in the RD mode. The

duration of this period is user controlled and must satisfy a

minimum of tP.

During this period S1, S3, S4 and S6 close, therefore

46pF of input capacitance must be charged up in addition

to the 11pF of stray capacitance.

1.3 TRACK AND HOLD vs. SAMPLE AND HOLD

The MSB Flash Converter of the ML2264 in T/H mode has

a track and hold mechanism for sampling the input. The

input is attached to the MSB comparators directly in the

MSB compare cycle, or acquisition period. When the MSB

compare cycle ends, the state of the MSB comparators is

latched. The LSB Flash Converter always performs a S/H

operation. Thus, the analog input signal can be changing

during the MSB compare cycle, or acquisition period, and

9

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