FAN5026 データシートの表示（PDF） - Fairchild Semiconductor

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FAN5026

Dual DDR/Dual-Output PWM Controller

Fairchild Semiconductor 

Circuit Description

Overview

The FAN5026 is a multi-mode, dual channel PWM con-

troller intended for graphic chipset, SDRAM, DDR DRAM

or other low output voltage power applications in PC’s,

VGA Cards and set top boxes. The IC integrates a con-

trol circuitry for two synchronous buck converters. The

output voltage of each controller can be set in the range

of 0.9V to 5.5V by an external resistor divider.

The two synchronous buck converters can operate from

either an unregulated DC source (such as a notebook

battery) with voltage ranging from 5.0V to 16V, or from a

regulated system rail of 3.3V to 5V. In either mode of

operation the IC is biased from a +5V source. The PWM

modulators use an average current mode control with

input voltage feed-forward for simplified feedback loop

compensation and improved line regulation. Both PWM

controllers have integrated feedback loop compen-

sation that dramatically reduces the number of external

components.

The FAN5026 can be configured to operate as a com-

plete DDR solution. When the DDR pin is set high, the

second channel can provide the capability to track the

output voltage of the first channel. The PWM2 converter

is prevented from going into hysteretic mode if the DDR

pin is set high. In DDR mode, a buffered reference volt-

age (buffered voltage of the REF2 pin), required by DDR

memory chips, is provided by the PG2 pin.

Converter Modes and Synchronization

Table 3. Converter Modes and Synchronization

Mode VIN

DDR

VIN Pin Pin

DDR1 Battery VIN

HIGH

DDR2 +5V R to GND HIGH

DUAL ANY VIN

LOW

PWM 2 w.r.t.

PWM1

IN PHASE

+ 90°

+ 180°

When used as a dual converter (as in Figure 5), out-of-

phase operation with 180 degree phase shift reduces

input current ripple.

For the “2-step” conversion (where the VTT is converted

from VDDQ as in Figure 4) used in DDR mode, the duty

cycle of the second converter is nominally 50% and the

optimal phasing depends on VIN. The objective is to

keep noise generated from the switching transition in one

converter from influencing the “decision” to switch in the

other converter.

When VIN is from the battery, it’s typically higher than

7.5V. As shown in Figure 6, 180° operation is undesir-

able since the turn-on of the VDDQ converter occurs

very near the decision point of the VTT converter.

CLK

VDDQ

VTT

Figure 6. Noise-Susceptible 180° Phasing for

DDR1

In-phase operation is optimal to reduce inter-converter

interference when VIN is higher than 5V, (when VIN is

from a battery), as can be seen in Figure 7. Since the

duty cycle of PWM1 (generating VDDQ) is short, its

switching point occurs far away from the decision point

for the VTT regulator, whose duty cycle is nominally 50%.

CLK

VDDQ

VTT

Figure 7. Optimal In-Phase Operation for DDR1

When VIN ≈ 5V, 180° phase shifted operation can be

rejected for the same reasons demonstrated Figure 6.

In-phase operation with VIN ≈ 5V is even worse, since

the switch point of either converter occurs near the

switch point of the other converter as seen in Figure 8. In

this case, as VIN is a little higher than 5V it will tend to

cause early termination of the VTT pulse width. Con-

versely, VTT’s switch point can cause early termination

of the VDDQ pulse width when VIN is slightly lower than

5V.

CLK

VDDQ

VTT

Figure 8. Noise-Susceptible In-Phase Operation

for DDR2

These problems are nicely solved by delaying the 2nd

converter's clock by 90° as shown in Figure 9. In this

way, all switching transitions in one converter take place

far away from the decision points of the other converter.

9

FAN5026 Rev. 1.0.5

www.fairchildsemi.com

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