MC10E445 MC100E445
Figure 3. Timing Diagrams
CLK
SIN
RESET
Q0
Q1
Q2
Q3
SOUT
CL/4
CL/8
Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3
Dn-4
Dn
Dn-3
Dn+1
Dn-2
Dn+2
Dn-1
Dn+3
Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3
Timing Diagram A. 1:4 Serial to Parallel Conversion
CLK
SIN
RESET
SYNC
Q0
Q1
Q2
Q3
SOUT
CL/4
CL/8
Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+4
Dn-4
Dn+1
Dn-3
Dn+2
Dn-2
Dn+3
Dn-1
Dn+4
Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+4
Timing Diagram B. 1:4 Serial to Parallel Conversion With SYNC Pulse
MOTOROLA
4
ECLinPS and ECLinPS Lite
DL140 — Rev 4