GMS34012 データシートの表示（PDF） - Hyundai Micro Electronics

部品番号

コンポーネント説明

メーカー

GMS34012

4-BIT SINGLE CHIP MICROCOMPUTERS

Hyundai Micro Electronics 

Chapter 2. Architecture

Initial Reset Circuit

RESET pin must be down to ¡ÈL¡È more than 4 machine cycle by outside

capacitor or other for power on reset.

The mean of 1 machine cycle is below. 1 machine cycle is 6/fOSC, however,

operating voltage must be in recommended operating conditions, and clock

oscillating stability.

* It is required to adjust C value depending on rising time of power supply.

(Example shows the case of rising time shorter than 10ms.)

1

0.1uF

RESET

Watch Dog Timer (WDT)

Watch dog timer is organized binary of 14 steps. By the selected oscillation

option, the signal of fOSC/6 cycle comes in the first step of WDT. If this counter

was overflowed, come out reset signal automatically, internal circuit is initialized.

The overflow time is 6¡¿2 13/fOSC (108.026ms at fOSC=455KHz.)

8¡¿6¡¿213/fOSC (108.026ms at fOSC = 3.64MHz)

Normally, the binary counter must be reset before the overflow by using reset

instruction (WDTR) or / and REMOUT port (Y-reg=8, So instruction execution) at

masked option.

* It is constantly reset in STOP mode. When STOP is released, counting is

restarted. (Refer to 2-10 STOP function>)

fOSC/6 or fOSC/48

Binary counter

(14 steps)

RESET (edge-trigger)

Reset

by instruction

REMOUT

output

Mask Option

CPU reset

2- 8

Share Link: