FS6131 データシートの表示（PDF） - ON Semiconductor

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FS6131

Programmable Line Lock Clock Generator IC

ON Semiconductor 

FS6131

fIN

Reference

Divider (NR)

fIN

fVCO

fOUT

?

Phase

Frequency

Detect

VCO

Feedback

Divider (NF)

Post

Divider (NF)

fVCO

fOUT

Figure 6: PLL with Post Divider

4.2.1. Clock Gobbler (Phase Adjust)

The clock gobbler circuit takes advantage of the unknown relationship between input and output clocks to permit the adjustment of the

CLKP/CLKN output clock phase relative to the REF input. The clock gobbler circuit removes a VCO clock pulse before the pulse clocks

the post divider. In this way, the phase of the output clock can be slipped until the output phase is aligned with the input clock phase.

To adjust the phase relationship, switch the feedback divider source to the post divider input via the FBKDSRC bit, and toggle the GBL

register bit. The clock gobbler output clock is delayed by one VCO clock period for each transition of the GBL bit from zero to one.

4.2.2. Phase Alignment

To maintain a fixed phase relation between input and output clocks, the post divider must be placed inside the feedback loop. The

source for the feedback divider is obtained from the output of the post divider via the FBKDSRC switch. In addition, the feedback divider

must be dividing at a multiple of the post divider.

fIN

Reference

Divider (NR)

fIN

fOUT

Phase

Frequency

Detect

VCO

Post

Divider (NF)

Feedback

Divider (NF)

Figure 7: Aligned I/O Phase

fOUT

4.2.3. Phase Sampling and Initial Alignment

However, the ability to adjust the phase is useless without knowing the initial relation between output and input phase. To aid in the

initial synchronization of the output phase to input phase, a phase align "flag" makes a transition (zero to one or one to zero) when the

output clock phase becomes aligned with the feedback source phase. The feedback source clock is, by definition, locked to the input

clock phase.

Rev. 4 | Page 6 of 44 | www.onsemi.com

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