FS6377
Table 6: Divider Control Bits
Name
Description
POST_A[3:0]
(Bits 99-96)
POST divider A (see Table 7)
POST_B[3:0]
(Bits 103-100)
POST divider B (see Table 7)
POST_C1[3:0]
(Bits 107-104)
POST divider C1 (see Table 7)
selected when the SEL_CD pin = 0
POST_C2[3:0]
(Bits 115-112)
POST divider C2 (see Table 7)
selected when the SEL_CD pin = 1
POST_D1[3:0]
(Bits 111-108)
POST divider D1 (see Table 7)
selected when the SEL_CD pin = 0
POST_D2[3:0]
(Bits 119-116)
POST divider D2 (see Table 7)
selected when the SEL_CD pin = 1
Table 7: Post Divider Modulus
BIT [3] BIT [2] BIT [1] BIT [0]
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Divide By
1
2
3
4
5
6
8
9
10
12
15
16
18
20
25
50
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