FS6377 データシートの表示（PDF） - ON Semiconductor
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FS6377 Datasheet PDF : 24 Pages
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FS6377
Table 13: AC Timing Specifications
Parameter
Symbol Conditions/Descriptions
Clock Min. Typ. Max.
(MHz)
Overall
Output frequency*
fO
VDD = 5.5V
VDD = 3.6V
0.8
150
0.8
100
VCO frequency*
fVCO
VDD = 5.5V
VDD = 3.6V
40
230
40
170
VCO gain*
AVCO
400
Loop filter time constant*
LFTC bit = 0
7
LFTC bit = 1
20
Rise time*
tr
VO = 0.5V to 4.5V; CL = 15pF
1.9
VO = 0.3V to 3.0V; CL = 15pF
1.6
Fall time*
Tristate enable delay*
tr
tPZL, tPZH
VO = 4.5V to 0.5V; CL = 15pF
VO = 3.0V to 0.3V; CL = 15pF
1.8
1.5
1
8
Tristate disable delay*
Clock stabilization time*
tPZL, tPZH
tSTB
Output active from power-up, via PD pin
After last register is written
1
8
100
1
Divider Modulus
Feedback divider
NF
See Table 2
8
2047
Reference divider
Post divider
NR
NP
See Table 8
1
255
1
50
Clock Outputs (PLL A clock via CLK_A pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge 100
45
55
to next falling edge at 2.5V) to one clock period
Jitter, long term (σy(τ))*
tj(LT)
On rising edges 500µs apart at 2.5V relative to an 100
45
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, no other PLLs active
On rising edges 500µs apart at 2.5V relative to an 50
165
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, all other PLLs active (B = 60MHz,
C = 40MHz, D = 14.318MHz)
Jitter, period (peak-peak)* tj(ΔP)
From rising edge to the next rising edge at 2.5V, 100
110
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, no other PLLs active
From rising edge to the next rising edge at 2.5V, 50
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, all other PLLs active (B = 60MHz,
C = 40MHz, D = 14.318MHz)
Clock Outputs (PLL B clock via CLK_B pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge 100
to next falling edge at 2.5V) to one clock period
Jitter, long term (σy(τ))*
tj(LT)
On rising edges 500µs apart at 2.5V relative to an 100
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, no other PLLs active
390
45
55
45
On rising edges 500µs apart at 2.5V relative to an 60
75
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, all other PLLs active (A = 50MHz,
C = 40MHz, D = 14.318MHz)
Jitter, period (peak-peak)* tj(ΔP)
From rising edge to the next rising edge at 2.5V, 100
120
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, no other PLLs active
From rising edge to the next rising edge at 2.5V, 60
400
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, all other PLLs active (A = 50MHz,
C = 40MHz, D = 14.318MHz)
Units
MHz
MHz
MHz/V
µs
ns
ns
ns
ns
µs
ms
%
ps
ps
%
ps
ps
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