FS6377 データシートの表示（PDF） - ON Semiconductor
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FS6377 Datasheet PDF : 24 Pages
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FS6377
Table 13: AC Timing Specifications continued
Clock Outputs (PLL_C clock via CLK_C pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge 100
45
55
%
to next falling edge at 2.5V) to one clock period
Jitter, long term (σy(τ))*
tj(LT)
On rising edges 500µs apart at 2.5V relative to an 100
45
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, no other PLLs active
ps
On rising edges 500µs apart at 2.5V relative to an 40
105
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, all other PLLs active (A = 50MHz,
B = 60MHz, D = 14.318MHz)
Jitter, period (peak-peak)* tj(ΔP)
From rising edge to the next rising edge at 2.5V, 100
120
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, no other PLLs active
ps
From rising edge to the next rising edge at 2.5V, 40
440
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, all other PLLs active (A = 50MHz,
B = 60MHz, D = 14.318MHz)
Clock Outputs (Crystal Oscillator via CLK_D pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge 14.318
45
55
%
to next falling edge at 2.5V) to one clock period
Jitter, long term (σy(τ))*
tj(LT)
On rising edges 500µs apart at 2.5V relative to an 14.318
20
ideal clock, CL = 15pF, fXIN = 14.318MHz, no other
PLLs active
ps
From rising edges to the next at 2.5V, CL = 15pF,
14.318
40
fXIN = 14.318MHz, all other PLLs active (A = 50MHz,
B = 60MHz, C = 40MHz)
Jitter, period (peak-peak)* tj(ΔP)
From rising edge to the next rising edge at 2.5V, 14.318
90
CL = 15pF, fXIN = 14.318MHz, no other PLLs active
From rising edge to the next rising edge at 2.5V,
ps
CL = 15pF, fXIN = 14.318MHz, all other PLLs active
14.318
450
(A = 50MHz, B = 60MHz, C = 40MHz)
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent
nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3σ from typical.
Table 14: Serial Interface Timing Specifications
Parameter
Symbol
Clock frequency
Bus free time between STOP and
START
Set-up time, START (repeated)
Hold time, START
Set-up time, data input
Hold time, data input
fSCL
tBUF
tsu:STA
tnd:STA
tsu:DAT
thd:DAT
Output data valid from clock
Rise time, data and clock
Fall time, data and clock
High time, clock
Low time, clock
Set-up time, STOP
tAA
tR
tF
tHI
tLO
Tsu:STO
Conditions/Description
SCL
SDA
SDA
Minimum delay to bridge undefined region of
the falling edge of SCL to avoid unintended
START or STOP
SDA, SCL
SDA, SCL
SCL
SCL
Standard Mode
Min.
Max.
0
100
4.7
4.7
4.0
250
0
3.5
1000
300
4.0
4.7
4.0
Units
kHz
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
µs
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*)
represent nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3σ from typical.
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