UPD75P048GC-AB8 データシートの表示（PDF） - NEC => Renesas Technology
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UPD75P048GC-AB8 Datasheet PDF : 40 Pages
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µPD75P048
SERIAL TRANSFER OPERATION
Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output)
Parameter
SCK Cycle Time
Symbol
Conditions
tKCY1
VDD = 4.5 to 6.0 V
SCK High-, Low-Level
tKL1
Widths
tKH1
SI Set-Up Time (vs. SCK ↑) tSIK1
SI Hold Time (vs. SCK ↑ ) tKSI1
SCK ↓→ SO Output
Delay Time
tKSO1
VDD = 4.5 to 6.0 V
RL = 1kΩ,
CL = 100pF
Note VDD = 4.5 to 6.0V
MIN. TYP.
1600
3800
tKCY1/2-50
tKCY1/2-150
150
400
MAX.
250
1000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input)
Parameter
SCK Cycle Time
Symbol
Conditions
tKCY2
VDD = 4.5 to 6.0V
SCK High-, Low-Level
tKL2
Widths
tKH2
SI Set-Up Time (vs. SCK ↑) tSIK2
SI Hold Time (vs. SCK ↑) tKSI2
SCK ↓→ SO Output
Delay Time
tKSO2
VDD = 4.5 to 6.0V
RL = 1kΩ, CL = 100 pF Note VDD = 4.5 to 6.0V
MIN.
800
3200
400
1600
100
400
Note RL and CL are load resistance and load capacitance of the SO output line.
TYP. MAX.
300
1000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
24
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