GS84118B-100 データシートの表示（PDF） - Giga Semiconductor

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GS84118B-100

256K x 18 Sync Cache Tag

Giga Semiconductor 

Pipeline—Read/Write Cycle Timing

GS84118T/B-166/150/130/100

CLK

ADSP

ADSC

ADV

A0–A17

GW

BWE

BW1–

BW4

CE1

CE2

CE3

OE

DQ1–16

DQP1–2

DE

Single Read

Single Write

Burst Read

tS tH

tS tH

tKH tKL

tKC

ADSP is blocked by CE1 inactive

tS tH

ADSC initiated read

tS tH

RD1

WR1

RD2

tS tH

tS

tH

tS tH

WR1

tS tH

CE1 masks ADSP

tS tH

CE2 and CE3 only sampled with ADSP and ADSC

tS tH

tOE

tOHZ

Deselected with CE3

Hi-Z

tKQ

tS tH

Q1a

D1a

tS tH

Q2a

Q2b

Q2c Q2d

Rev: 1.05 7/2001

19/30

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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