GS9021A データシートの表示（PDF） - Gennum -> Semtech
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GS9021A Datasheet PDF : 26 Pages
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TABLE 2: GS9021A Case Table
MODE
CASE
NUMBER
R/T
CRC_MODE
EDH
PACKET
RESULTS
COMMENTS / SUGGESTIONS
TX MODE
1
0
0
2
0
0
NO
No EDH comparison is performed. Use this MODE if you wish to
A new EDH packet is inserted into insert EDH if it is not present. If
YES
the data stream with all the EDH
EDH is present, clear all flags and
flags cleared unless overwritten by update CRC.
the dedicated flag port or the host
interface. The EDH packet will
include CRC values calculated
from the data stream.
CRC MODE
3
X
1
4
X
1
NO
Same results as Case #1
Use this MODE on the output EDH
chip when mapping flags from an
YES
No EDH comparison is performed input EDH chip around a
(i.e. no attempt is made to detect processing core (which would
errors). The CRC is updated and
alter the picture data) to an output
all flags preserved or unaltered
unless overwritten by the
dedicated flag port or host
interface.
EDH chip so that EDH errors are
not generated. You can also use
this mode when you simply want
to update the CRC values after
processing, if the processing
does not corrupt the EDH packet.
In both cases, the EDH flags are
preserved.
RX MODE
5
1
0
NO
New EDH packet inserted into
Use this MODE when you wish to
data stream with all error flags
detect errors in the data stream,
cleared and all UES flags set high or on an input EDH chip when
unless overwritten by the
mapping flags around a
dedicated flag port or the host
processing core (that would alter
interface.
the picture data) to an output EDH
chip so that EDH errors are not
generated due to the data
processing.
6
1
0
YES
EDH comparison performed and
Use this MODE when you want to
error flags set and mapped
insert EDH if it is not present or
appropriately unless overwritten
update CRC values and preserve
by the dedicated flag port or the
the flags in an existing EDH
host interface. The CRC is
packet.
updated and the EDH packet is re-
inserted.
NOTE
1. “X” in the table above means ‘don’t care’ (but not left floating).
DIN [9:0]
DOUT [9:0]
PCLK IN
1
2
3
4
5
6
7
8
1
2
3
tLAT
Fig. 3 Data Latency through the GS9021A
18 of 26
19983 - 1
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