HD64F2370 データシートの表示（PDF） - Renesas Electronics

部品番号

コンポーネント説明

メーカー

HD64F2370

16-Bit Single-Chip Microcomputer

Renesas Electronics 

Item

6.6.1 Setting DRAM

Space

Table 6.4 Relation

between Settings of

Bits RMTS2 to RMTS0

and DRAM Space

9.2.7 DTC Enable

Registers A to H

(DTCERA to DTCERH)

Section 10 I/O Ports

Table 10.1 Port

Functions

10.1.4 Pin Functions

10.2.4 Pin Functions

10.3.6 Pin Functions

10.6.4 Pin Functions

10.14.1 Port F Data

Direction Register

(PFDDR)

10.14.4 Pin Functions

Page

191

430

456 to

460

462

474

487

496

529

533,

534

Revision (See Manual for Details)

Note * amended

Note: * Reserved (setting prohibited) in the H8S/2378 Group.

Description of DTC Activation Enable amended

[Clearing conditions] ... These bits are not automatically cleared

when the DISEL bit is 0 and specified number of transfers have

not ended

• When 0 is written to DTCE after reading DTCE = 1

Table 10.1 amended

Mode 1*3 Mode 2*3

Note 1 amended

Note: 1. Not supported by the H8S/2378 0.18µm F-ZTAT Group,

H8S/2377, H8S/2375, and H8S/2373.

Title amended

Title amended

Mode 7 (EXPE = 0)

Note 3 amended

Note: 3. Not used in the H8S/2378 0.18µm F-ZTAT Group,

H8S/2377, H8S/2375, and H8S/2373.

Title amended

Subheading deleted

• PF2/LCAS/IRQ15/DQML

• PF1/UCAS/IRQ14/DQMU

Note 2 amended

Note: 2. Not used in the H8S/2378 0.18µm F-ZTAT Group,

H8S/2377, H8S/2375, and H8S/2373.

Rev. 6.00 Jul 19, 2006 page x of lxiv

Share Link: