HD6432676 データシートの表示（PDF） - Renesas Electronics

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HD6432676

16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Renesas Electronics 

8.3.4 EXDMA Mode Control Register (EDMDR) ....................................................... 341

8.3.5 EXDMA Address Control Register (EDACR) .................................................... 346

8.4 Operation .......................................................................................................................... 350

8.4.1 Transfer Modes .................................................................................................... 350

8.4.2 Address Modes .................................................................................................... 351

8.4.3 DMA Transfer Requests ...................................................................................... 355

8.4.4 Bus Modes ........................................................................................................... 355

8.4.5 Transfer Modes .................................................................................................... 357

8.4.6 Repeat Area Function .......................................................................................... 359

8.4.7 Registers during DMA Transfer Operation.......................................................... 361

8.4.8 Channel Priority Order......................................................................................... 366

8.4.9 EXDMAC Bus Cycles (Dual Address Mode)...................................................... 369

8.4.10 EXDMAC Bus Cycles (Single Address Mode) ................................................... 376

8.4.11 Examples of Operation Timing in Each Mode .................................................... 380

8.4.12 Ending DMA Transfer ......................................................................................... 393

8.4.13 Relationship between EXDMAC and Other Bus Masters ................................... 394

8.5 Interrupt Sources............................................................................................................... 395

8.6 Usage Notes ...................................................................................................................... 398

8.6.1 EXDMAC Register Access during Operation ..................................................... 398

8.6.2 Module Stop State................................................................................................ 398

8.6.3 EDREQ Pin Falling Edge Activation................................................................... 398

8.6.4 Activation Source Acceptance ............................................................................. 399

8.6.5 Enabling Interrupt Requests when IRF = 1 in EDMDR ...................................... 399

8.6.6 ETEND Pin and CBR Refresh Cycle................................................................... 399

Section 9 Data Transfer Controller (DTC)................................................................... 401

9.1 Features ............................................................................................................................. 401

9.2 Register Descriptions ........................................................................................................ 402

9.2.1 DTC Mode Register A (MRA) ............................................................................ 403

9.2.2 DTC Mode Register B (MRB)............................................................................. 404

9.2.3 DTC Source Address Register (SAR).................................................................. 405

9.2.4 DTC Destination Address Register (DAR).......................................................... 405

9.2.5 DTC Transfer Count Register A (CRA) .............................................................. 405

9.2.6 DTC Transfer Count Register B (CRB)............................................................... 405

9.2.7 DTC Enable Registers A to G (DTCERA to DTCERG) ..................................... 405

9.2.8 DTC Vector Register (DTVECR)........................................................................ 406

9.3 Activation Sources ............................................................................................................ 407

9.4 Location of Register Information and DTC Vector Table ................................................ 408

9.5 Operation .......................................................................................................................... 410

9.5.1 Normal Mode....................................................................................................... 412

9.5.2 Repeat Mode ........................................................................................................ 413

Rev. 3.00 Mar 17, 2006 page xix of l

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