HD404848 データシートの表示（PDF） - Hitachi -> Renesas Electronics

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HD404848

4-Bit Single-Chip Microcomputer

Hitachi -> Renesas Electronics 

HD404849 Series

Table 3 Interrupt Processing and Activation Conditions

Interrupt Source

Interrupt Control Bit

INT0

IE

1

INT1

1

Timer A

1

Timer B

or INT2

1

Timer C

or INT3

1

Timer D

1

IF0 • IM0

1

0

0

0

0

0

IF1 • IM1

*

1

0

0

0

0

IFTA • IMTA

*

*

1

0

0

0

IFTB • IMTB + IF2 • IM2 *

*

*

1

0

0

IFTC • IMTC + IF3 • IM3 *

*

*

*

1

0

IFTD • IMTD

*

*

*

*

*

1

IFAD • IMAD + IFS • IMS *

*

*

*

*

*

Note: Bits marked * can be either 0 or 1. Their values have no effect on operation.

A/D or

Serial

1

0

0

0

0

0

0

1

Instruction cycles

1

2

3

4

5

6

Instruction

execution*

Interrupt

acceptance

Stacking

IE reset

Vector address

generation

Execution of JMPL

instruction at vector address

Note: * The stack is accessed and the IE reset after the instruction

is executed, even if it is a two-cycle instruction.

Figure 10 Interrupt Processing Sequence

Execution of

instruction at

start address

of interrupt

routine

21

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