HD74LS166A データシートの表示（PDF） - Renesas Electronics

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HD74LS166A

8-bit Shift Register

Renesas Electronics 

HD74LS166A

Waveform

Notes:

tw (Clear)

3V

Clear

Input

1.3V

1.3V

tn tn + 1

0V

tn tn + 1

3V

Clock 1.3V

Input

1.3V

1.3V

1.3V

0V

tw (Clock)

tsu th

tsu th

3V

Data

Input

Output QH

1.3V

tPHL

1.3V

1.3V

1.3V

1.3V

0V

tPLH

tPHL

VOH

1.3V

1.3V

VOL

1. Input pulse; ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle 50%

Clock input; tw ≥ 20 ns

Clear inpu; tw ≥ 20 ns, th = 10 ns, when testing ƒmax, vary the clock PRR.

2. Propagation delay time (tPLH and tPHL) are measured at tn + 1. Proper shifting of data is verified

at tn + 8 with a functional test.

3. tn; bit time before clocking transition.

tn + 1; bit time after one clocking transition.

tn + 8; bit time after eight clocking transition.

Typical Clear, Shift, Load, Inhibit, and Shift Sequences

Clock

Clock Inhibit

Clear

Serial Input

Shift / Load

A

B

C

Parallel D

Inputs E

F

G

H

Output QH

H

L

H

L

H

L

H

H

HH L H LH L H L

Clear

Serial Shift

Load Inhibit

Serial Shift

Rev.4.00, May 10, 2006, page 6 of 7

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