HD74LV166AFPEL(2004) データシートの表示（PDF） - Renesas Electronics
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HD74LV166AFPEL Datasheet PDF : 10 Pages
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HD74LV166A
Function Table
Inputs
Internal outputs
CLR
SH/LD
CLK INH CLK
SER
A ... H
QA
QB
L
X
X
X
X
X
L
L
H
X
L
L
X
X
QA0
QB0
H
L
L
↑
X
a ... h
a
b
H
H
L
↑
H
X
H
QAn
H
H
L
↑
L
X
L
QAn
H
X
H
↑
X
X
QA0
QB0
Note: H: High level
L: Low level
↑: Low to high transition
X: Immaterial
a ... h: Parallel data
QA0 ... QH0: Outputs remain unchanged.
QAn ... QGn: Data shifted from the previous stage on a positive edge at the clock input.
Pin Arrangement
Output
QH
L
QH0
h
QGn
QGn
QH0
SER 1
A2
B3
C4
D5
CLK INH 6
CLK 7
GND 8
(Top view)
16 VCC
15 SH/LD
14 H
13 QH
12 G
11 F
10 E
9 CLR
Rev.3.00 Jun. 04, 2004 page 2 of 9
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