HDM8513 データシートの表示（PDF） - Hynix Semiconductor

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HDM8513

DVB/DSS Compliant Receiver

Hynix Semiconductor 

Table 6: Intel 80C88A Write Cycle Timing Parameters (Busmode = 1)

Symbol

tsu1

th1

tpw1

td1

tdoz1

Parameter

Input Data Setup before /WE Inactive

Input Address, Data and /CE Hold after /WE Inactive

/WE Low Duration

Delay from /CE to DTACK Active

Delay from /WE Inactive to DTACK in Tristate Mode

Min. Max. Unit

20

-

ns

8

-

ns

200 -

ns

-

35 ns

-

15 ns

HI_ADDR [4:0]

/CE

/WE

DTACK

Valid

tpw1

td1

th1

tdoz1

HI_DATA[7:0]

tsu1

FIGURE 4: INTEL 80C88A WRITE TIMING DIAGRAM

Note: HI_ADDR[4:0] is derived from the processor(80C88A) A15-A8 bus and HI_DATA[7:0] is

connected to the AD7 - AD0 bus.

#This page is only for HDM8513AP.

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