HDM8515 データシートの表示（PDF） - Hynix Semiconductor

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コンポーネント説明

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HDM8515

DVB/DSS Compliant Receiver

Hynix Semiconductor 

DATA_CLK

DATA_STB

tsu

t hd

FRAME_SYNC

DATA_VALID

DATA

n-3 n-2 n-1 n xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx 1 2 3 4

FIGURE 11: OUTPUT TIMING DIAGRAM FOR REGULATED PARALLEL

DATA_CLK

tsu

t hd

DATA_STB

FRAME_SYNC

DATA_VALID

DATA [0] 8n-8 xx xx 8n-7 8n-68n-5 8n-4 xx 8n-3 8n-28n-1 8n xx xx xx xx xx xx xx xx 1 2 3 4

FIGURE 12: OUTPUT TIMING DIAGRAM FOR REGULATED SERIAL

NOTE : In case of DVB, n is 188

In case of DSS, n is 144

18

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