HIP6602B データシートの表示（PDF） - Intersil

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HIP6602B

Dual Channel Synchronous Rectified Buck MOSFET Driver

Intersil 

HIP6602B

ensure safe operation at the desired frequency for the

selected MOSFETs. The total chip power dissipation is

approximated as:

[ ] P = 1.05 x fSW x VPVCC

3_

2

(QU1

+

QU2)

+

(QL1

+

QL2)

+ IDDQ x VCC

where fsw is the switching frequency of the PWM signal. QU

and QL is the upper and lower gate charge determined by

MOSFET selection and any external capacitance added to

the gate pins. The IDDQ VCC product is the quiescent power

of the driver and is typically 40mW.

The 1.05 term is a correction factor derived from the

following characterization. The base circuit for characterizing

the drivers for different loading profiles and frequencies is

provided. CU and CL are the upper and lower gate load

capacitors. Decoupling capacitors [0.15µF] are added to the

PVCC and VCC pins. The bootstrap capacitor value in the

test circuit is 0.01µF.

The power dissipation approximation is a result of power

transferred to and from the upper and lower gates. But, the

internal bootstrap device also dissipates power on-chip

during the refresh cycle. Expressing this power in terms of

the upper MOSFET total gate charge is explained below.

The bootstrap device conducts when the lower MOSFET or

its body diode conducts and pulls the PHASE node toward

GND. While the bootstrap device conducts, a current path is

formed that refreshes the bootstrap capacitor. Since the

upper gate is driving a MOSFET, the charge removed from

the bootstrap capacitor is equivalent to the total gate charge

of the MOSFET. Therefore, the refresh power required by

the bootstrap capacitor is equivalent to the power used to

charge the gate capacitance of the upper MOSFETs.

PREFRESH

=

fSWQLOSSVPVCC

=

fSW

QU

V

P

V

C

C

where QLOSS is the total charge removed from the bootstrap

capacitors and provided to the upper gate loads.

In Figure 2, CU and CL values are the same and frequency

is varied from 10kHz to 1.5MHz. PVCC and VCC are tied

together to a +12V supply.

Figure 3 shows the dissipation in the driver with 1nF loading

on both gates and each individually. Figure 4 is the same as

Figure 3 except the capacitance is increased to 3nF.

The impact of loading on power dissipation is shown in

Figure 5. Frequency is held constant while the gate

capacitors are varied from 1nF to 5nF. VCC and PVCC are

tied together and to a +12V supply. Figures 6, 7 and 8 show

the same characterization for PVCC tied to +5V instead of

+12V. The gate supply voltage, PVCC, within the HIP6602B

sets both upper and lower gate driver supplies at the same

5V level for the last three curves.

Test Circuit

+5V OR +12V

+12V

+5V OR +12V

0.01µF

PVCC

0.15µF

VCC

BOOT1

UGATE1

PHASE1

2N7002

CU

0.15µF

PWM1

PGND

LGATE1

2N7002

CL

0.01µF

100kΩ

GND

PWM2

BOOT2

UGATE2

PHASE2

2N7002

CU

LGATE2

2N7002

CL

100kΩ

FIGURE 1. HIP6602B TEST CIRCUIT

8

FN9076.5

July 22, 2005

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