HM62256BLFP-7T データシートの表示（PDF） - Hitachi -> Renesas Electronics

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HM62256BLFP-7T

256k SRAM (32-kword × 8-bit)

Hitachi -> Renesas Electronics 

HM62256B Series

Low VCC Data Retention Characteristics (Ta = 0 to 70°C)

Parameter

Symbol Min

Typ*1 Max

Unit

Test conditions*6

VCC for data retention

VDR

2.0

—

5.5

V

CS ≥ VCC – 0.2 V,

Vin ≥ 0V

Data retention current

I CCDR

—

0.05

30*2

µA

VCC = 3.0 V, Vin ≥ 0V

CS ≥ VCC – 0.2 V

I CCDR

—

0.05

10*3

µA

I CCDR

—

0.05

3*4

µA

Chip deselect to data

t CDR

0

—

—

ns

See retention Waveform

retention time

Operation recovery time tR

t RC* 5

—

—

ms

Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed.

2. 10 µA max. at Ta = 0 to +40°C.

3. This characteristic is guaranteed only for L-SL version, 3 µA max. at Ta = 0 to +40°C.

4. This characteristic is guaranteed only for L-UL version, 0.6 µA max. at Ta = 0 to +40°C.

5. tRC = Read cycle time.

6. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data retention

mode, Vin levels (address, WE, OE, I/O) can be in the high impedance state.

Low VCC Data Retention Timing Waveform

VCC

4.5V

2.2V

VDR

CS

0V

tCDR

Data retention mode

tR

CS ≥ VCC − 0.2V

12

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