HM628512B データシートの表示（PDF） - Hitachi -> Renesas Electronics

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HM628512B

4 M SRAM (512-kword x 8-bit)

Hitachi -> Renesas Electronics 

HM628512B Series

Low VCC Data Retention Characteristics (Ta = –20 to +70°C)

Parameter

Symbol Min Typ Max Unit Test conditions*4

VCC for data retention

Data retention current

VDR

I CCDR

2

——

V

—

1*5 50*1 µA

—

1*5 15*2 µA

CS ≥ VCC – 0.2 V, Vin ≥ 0 V

VCC = 3.0 V, Vin ≥ 0 V

CS ≥ VCC – 0.2 V

—

1*5 10*3 µA

Chip deselect to data retention time tCDR

0

——

ns

See retention waveform

Operation recovery time

tR

tRC*6 —

—

ns

Notes: 1. For L-version and 20 µA (max.) at Ta = –20 to +40°C.

2. For L-SL-version and 3 µA (max.) at Ta = –20 to +40°C.

3. For L-UL-version and 3 µA (max.) at Ta = –20 to +40°C.

4. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin

levels (address, WE, OE, I/O) can be in the high impedance state.

5. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.

6. tRC = read cycle time.

Low VCC Data Retention Timing Waveform (CS Controlled)

tCDR

Data retention mode

tR

VCC

4.5 V

2.2 V

VDR

CS

0V

CS ≥ VCC – 0.2 V

12

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