HT46R14A データシートの表示（PDF） - Holtek Semiconductor

部品番号

コンポーネント説明

メーカー

HT46R14A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R14A

of INTC0 and INTC1 may be set to allow interrupt nest-

ing. If the stack is full, the interrupt request will not be ac-

knowledged, even if the related interrupt is enabled, until

the stack pointer is decremented. If immediate service is

desired, the stack must be prevented from becoming full.

All these kind of interrupts have a wake-up capability. As

an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack, followed by

a branch to a subroutine at specified location in the pro-

gram memory. Only the program counter is pushed onto

the stack. If the contents of the register or status register

are altered by the interrupt service program which cor-

rupts the desired control sequence, the contents should

be saved in advance.

External interrupts are triggered by a high to low transi-

tion of INT0, INT1 or PC1/COVIN+, and the related in-

terrupt request flag (EI0F; bit 4 of the INTC0, EI1F; bit 5

of the INTC0, EI2F; bit 5 of the INTC1) is set as well. Af-

ter the interrupt is enabled, the stack is not full, and the

external interrupt is active, a subroutine call to location

04H or 08H occurs. The interrupt request flag (EI0F,

EI1F or EI2F) and EMI bits are all cleared to disable

other interrupts.

The comparator output Interrupt is initialized by setting

the comparator 0 output Interrupt request flag (C0F) or

comparator 1 output interrupt request flag (C1F), which

is caused by a falling edge transition of comparator 0 or

comparator 1 output . After the interrupt is enabled, and

the stack is not full, and the interrupt request flag (C0F

or C1F bit) is set, a subroutine call to location 0CH/10H

occurs. The related interrupt request flag (C0F or C1F)

is reset, and the EMI bit is cleared to disable further in-

terrupts.

The Multi-Function Interrupt (MFI) is initialized by set-

ting the interrupt request flag (MFF), that is caused by

timer 0 overflow (T0F) , timer 1 overflow (T1F) or ADC

conversion completed (ADF). After the interrupt is en-

abled (EMFI=1), the stack is not full, and the MFF bit is

set, a subroutine call to location 018H will occur. The re-

lated interrupt request flag (MFF) is reset and the EMI bit

is cleared to disable further interrupts. T0F, T1F and

ADF indicate that a related interrupt has occurred.

These flags will not be cleared automatically after read-

ing these flags and should be cleared by user.

Bit No.

0

1

2

3

4

5

6

7

Label

EMI

EEI0

EEI1

EC0I

EI0F

EI1F

C0F

¾

Function

Controls the master (global) interrupt (1=enable; 0=disable)

Controls the external interrupt 0 (1=enable; 0=disable)

Controls the external interrupt 1 (1=enable; 0=disable)

Control the Comparator 0 interrupt (1= enable; 0= disable)

External interrupt 0 request flag (1=active; 0=inactive)

External interrupt 1 request flag (1=active; 0=inactive)

The Comparator 0 request flag (1=active; 0=inactive)

For test mode used only.

Must be written as ²0²; otherwise may result in unpredictable operation.

INTC0 (0BH) Register

Bit No.

0

1

2

3

4

5

6

7

Label

EC1I

EEI2

EMFI

¾

C1F

EI2F

MFF

¾

Function

Control the Comparator 1 interrupt (1=enabled; 0=disabled)

Control the external interrupt 2 (1=enabled; 0=disabled)

Control the multi-function interrupt (1=enabled; 0=disabled)

Unused bit, read as ²0²

The Comparator 1 request flag (1=active; 0=inactive)

External interrupt 2 request flag (1=active; 0=inactive)

Multi-function request flag

Unused bit, read as ²0²

INTC1 (1EH) Register

Rev. 1.00

10

August 3, 2007

Share Link: