HT46R14A データシートの表示（PDF） - Holtek Semiconductor

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HT46R14A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R14A

eration. In other words, a dummy period will be inserted

after the wake-up. If the wake-up results from an inter-

rupt acknowledge, the actual interrupt subroutine exe-

cution will be delayed by one or more cycles. If the

wake-up results in the next instruction execution, this

will be executed immediately after the dummy period is

finished.

To minimise power consumption, all the I/O pins should

be carefully managed before entering the Power-down

mode.

Reset

There are three ways in which a reset can occur:

· RES pin reset during normal operation

· RES pin reset during Power-down

· WDT time-out reset during normal operation

The WDT time-out during a Power-down is different

from other device reset conditions, since it can perform

a ²warm reset² that resets only the program counter and

the SP, leaving the other circuits in their original state.

Some registers remain unchanged during other reset

conditions. Most registers are reset to the ²initial condi-

tion² when the reset conditions are met. By examining

the PDF and TO flags, the program can distinguish be-

tween different ²chip resets².

TO PDF

RESET Conditions

0 0 RES reset during power-up

u u RES reset during normal operation

0 1 RES wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² means unchanged

To guarantee that the system oscillator is started and

stabilised, the SST (System Start-up Timer) provides an

extra delay of 1024 system clock pulses when the sys-

tem reset (power-up, WDT time-out or RES reset) or the

system awakes from the Power-down state.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from a

Power-down will enable the SST delay.

An extra option load time delay is added during a system

reset (power-up, WDT time-out at normal mode or RES

reset).

VDD

RES

tS S T

S S T T im e - o u t

C h ip R e s e t

Reset Timing Chart

The functional unit chip reset status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler, Divider

Cleared

WDT

Clear. After master reset,

WDT begins counting

Timer/Event Counter Off

PPG Timer

Off

PPG output

Floating

Input/Output Ports Input mode

Stack Pointer

Points to the top of the stack

V DD

100kW

0 .1 m F

RES

B a s ic

R eset

C ir c u it

V DD

0 .0 1 m F

100kW

10kW

0 .1 m F

RES

H i-n o is e

R eset

C ir c u it

Reset Circuit

Note: Most applications can use the Basic Reset Circuit

as shown, however for applications with extensive noise,

it is recommended to use the Hi-noise Reset Circuit.

H A LT

W DT

W a rm R e s e t

RES

O SC1

SST

1 0 - b it R ip p le

C o u n te r

C o ld

R eset

S y s te m R e s e t

Reset Configuration

Rev. 1.00

13

August 3, 2007

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