HT46C232 データシートの表示（PDF） - Holtek Semiconductor
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HT46C232 Datasheet PDF : 50 Pages
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HT46R232/HT46C232
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first exam-
ple, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr EADI
; disable ADC interrupt
mov a,00000001B
mov ACSR,a
mov a,00100000B
; setup the ACSR register to select fSYS/8 as the A/D clock
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov ADCR,a
; and select AN0 to be connected to the A/D converter
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr START
set START
; reset A/D
clr START
; start A/D
Polling_EOC:
sz EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp polling_EOC
; continue polling
mov a,ADRH
; read conversion result high byte value from the ADRH register
mov adrh_buffer,a
; save result to user defined memory
mov a,ADRL
; read conversion result low byte value from the ADRL register
mov adrl_buffer,a
; save result to user defined memory
:
:
jmp start_conversion
; start next A/D conversion
Example: using interrupt method to detect end of conversion
clr EADI
; disable ADC interrupt
mov a,00000001B
mov ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov a,00100000B
mov ADCR,a
:
:
Start_conversion:
clr START
set START
clr START
clr ADF
set EADI
set EMI
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov acc_stack,a
mov a,STATUS
mov status_stack,a
:
:
mov a,ADRH
mov adrh_buffer,a
mov a,ADRL
mov adrl_buffer,a
clr START
set START
clr START
:
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a
mov a,acc_stack
reti
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
; reset A/D
; start A/D
; clear ADC interrupt request flag
; enable ADC interrupt
; enable global interrupt
; save ACC to user defined memory
; save STATUS to user defined memory
; read conversion result high byte value from the ADRH register
; save result to user defined register
; read conversion result low byte value from the ADRL register
; save result to user defined register
; reset A/D
; start A/D
; restore STATUS from user defined memory
; restore ACC from user defined memory
Rev. 1.40
21
November 23, 2005
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