HT46C24 データシートの表示（PDF） - Holtek Semiconductor
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HT46C24 Datasheet PDF : 51 Pages
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HT46R24/HT46C24
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
Modulation cycle i
(i=0~3)
AC (0~3)
i<AC
i³AC
Duty Cycle
DC+ 1
64
DC
64
A (7+1) bits mode PWM cycle is divided into two modu-
lation cycles (modulation cycle0~modulation cycle 1).
Each modulation cycle has 128 PWM input clock period.
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1. The group 2 is denoted by AC which is
the value of PWM.0.
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
Modulation cycle i
(i=0~1)
AC (0~1)
i<AC
i³AC
Duty Cycle
DC+ 1
128
DC
128
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
PWM
PWM Cycle PWM Cycle
Modulation Frequency Frequency Duty
fSYS/64 for (6+2) bits mode
fSYS/128 for (7+1) bits mode
fSYS/256
[PWM]/256
A/D Converter
The 8 channels and 10-bit resolution A/D converter are
implemented in this microcontroller. The reference volt-
age is VDD. The A/D converter contains 4 special regis-
ters which are; ADRL (24H), ADRH (25H), ADCR (26H)
and ACSR (27H). The ADRH and ADRL are A/D result
register higher-order byte and lower-order byte and are
read-only. After the A/D conversion is completed, the
ADRH and ADRL should be read to get the conversion
result data. The ADCR is an A/D converter control regis-
ter, which defines the A/D channel number, analog
channel select, start A/D conversion control bit and the
end of A/D conversion flag. If the users want to start an
A/D conversion, define PB configuration, select the con-
verted analog channel, and give START bit a raising
edge and falling edge (0®1®0). At the end of A/D con-
version, the EOCB bit is cleared and an A/D converter
interrupt occurs (if the A/D converter interrupt is en-
abled). The ACSR is A/D clock setting register, which is
used to select the A/D clock source.
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of eight
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled and the A/D
converter circuit is power on. The EOCB bit (bit6 of the
ADCR) is end of A/D conversion flag. Check this bit to
know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of the
A/D converter. Giving START bit a rising edge and fall-
ing edge means that the A/D conversion has started. In
order to ensure the A/D conversion is completed, the
START should remain at ²0² until the EOCB is cleared to
²0² (end of A/D conversion).
Bit No. Label
Function
Selects the A/D converter clock
source
0 ADCS0 00= system clock/2
1 ADCS1 01= system clock/8
10= system clock/32
11= undefined
2~6
¾ Unused bit, read as ²0²
7
TEST For test mode used only
ACSR (27H) Register
Bit No. Label
Function
0
ACS0
1
ACS1 Defines the analog channel select
2
ACS2
3
4
5
PCR0
PCR1
PCR2
Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is
power off to reduce power consumption
Indicates end of A/D conversion. (0 = end of A/D conversion)
6
EOCB Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, other-
wise the EOCB flag may have an undefined condition. See ²Important note for A/D initialization².
7 START Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)
ADCR (26H) Register
Rev. 2.00
19
March 2, 2006
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