HT46C24 データシートの表示（PDF） - Holtek Semiconductor
部品番号
コンポーネント説明
メーカー
HT46C24 Datasheet PDF : 51 Pages
| |||
HT46R24/HT46C24
PCR2 PCR1 PCR0
7
6
5
4
3
2
1
0
0
0
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
0
1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
AN0
0
1
0
PB7
PB6
PB5
PB4
PB3
PB2
AN1
AN0
0
1
1
PB7
PB6
PB5
PB4
PB3
AN2
AN1
AN0
1
0
0
PB7
PB6
PB5
PB4
AN3
AN2
AN1
AN0
1
0
1
PB7
PB6
PB5
AN4
AN3
AN2
AN1
AN0
1
1
0
PB7
PB6
AN5
AN4
AN3
AN2
AN1
AN0
1
1
1
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Port B Configuration
ACS2
0
0
0
0
1
1
1
1
ACS1
0
0
1
1
0
0
1
1
ACS0
0
1
0
1
0
1
0
1
Analog Input Channel Selection
Analog Channel
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Bit 7 of the ACSR register is used for test purposes only and must not be used for other purposes by the application pro-
gram. Bit1 and bit0 of the ACSR register are used to select the A/D clock source.
When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to ²1² when the
START bit is set from ²0² to ²1².
Important Note for A/D initialization:
Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits are modified,
otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented by setting the START
bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note
that if the Port B channel selection bits are all cleared to zero then an A/D initialization is not required.
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADRL
D1
D0
¾
¾
¾
¾
¾
¾
ADRH
D9
D8
D7
D6
D5
D4
D3
D2
Note: D0~D9 is A/D conversion result data bit LSB~MSB.
ADRL (24H), ADRH (25H) Register
Rev. 2.00
20
March 2, 2006
Share Link: 