HT46R32 データシートの表示（PDF） - Holtek Semiconductor

部品番号

コンポーネント説明

メーカー

HT46R32

A/D Type 8-Bit OTP MCU with OPA

Holtek Semiconductor 

HT46R32/HT46R34

is stopped, but the WDT oscillator keeps running with a

period of approximately 65ms at 5V. The WDT oscillator

can be disabled by a configuration option to conserve

power.

Watchdog Timer - WDT

The WDT clock source comes from either its own inte-

grated RC oscillator, known as the WDT oscillator, or the

instruction clock, which is the system clock divided by 4.

The choice of which one is used is decided by a

configuration option. This timer is designed to prevent a

software malfunction or sequence from jumping to an

unknown location with unpredictable results. The

Watchdog Timer can be disabled by a configuration op-

tion. If the Watchdog Timer is disabled, all the execu-

tions related to the WDT result in no operation.

Once the internal WDT oscillator (RC oscillator with a

period of 65ms at 5V nominal) is selected, it is divided by

32768~65536 to get a time-out period of approximately

2.1s~4.3s. This time-out period may vary with tempera-

tures, VDD and process variations. If the WDT oscillator

is disabled, the WDT clock may still come from the in-

struction clock and operate in the same manner except

that in the Power-down state the WDT may stop count-

ing and lose its protecting purpose. In this situation the

logic can only be restarted by external logic.

If the device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT instruction will stop the system

clock.

The WDT overflow under normal operation will initialise

a ²chip reset² and set the status bit ²TO². But in the

Power-down mode, the overflow will initialisze a ²warm

reset², and only the program counter and SP are reset to

zero. To clear the contents of the WDT, three methods

are adopted; external reset (a low level on the RES pin),

a software instruction and a HALT instruction. The soft-

ware instruction include ²CLR WDT² and the other set -

²CLR WDT1² and ²CLR WDT2². Of these two types of

instruction, only one can be active depending on the

configuration option - ²CLR WDT times selection op -

tion². If the ²CLR WDT² is selected (i.e. CLR WDT times

equal one), any execution of the ²CLR WDT² instruction

will clear the WDT. In the case that ²CLR WDT1² and

²CLR WDT2² are chosen (i.e. CLR WDT times equal

two), these two instructions must be executed to clear

the WDT; otherwise, the WDT may reset the chip as a

result of time-out.

Power Down Operation - HALT

The HALT mode is initialised by the ²HALT² instruction

and results in the following...

· The system oscillator will be turned off but the WDT

oscillator keeps running (if the WDT oscillator is se-

lected).

· The contents of the on chip Data Memory and regis-

ters remain unchanged.

· WDT will be cleared and start counting again (if the

WDT clock is from the WDT oscillator).

· All of the I/O ports maintain their original status.

· The PDF flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialisation and the WDT overflow per-

forms a ²warm reset². After the TO and PDF flags are

examined, the reason for the chip reset can be deter-

mined. The PDF flag is cleared by a system power-up or

executing the ²CLR WDT² instruction and is set when

executing the ²HALT² instruction. The TO flag is set if

the WDT time-out occurs, and causes a wake-up that

only resets the program counter and Stack Pointer; the

others keep their original status.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake up the

device by the options. Awakening from an I/O port stim-

ulus, the program will resume execution of the next in-

struction. If it is awakening from an interrupt, two

sequences may happen. If the related interrupt is dis-

S y s te m C lo c k /4

W DT

O SC

O p tio n fS 8 - b it C o u n te r

S e le c t

7 - b it C o u n te r

Watchdog Timer

T

T

W D T T im e - o u t

fS /2 1 5~ fS /2 1 6

C LR W D T

Rev. 1.10

11

March 16, 2007

Share Link: