HT46R52-18 データシートの表示（PDF） - Holtek Semiconductor
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HT46R52-18 Datasheet PDF : 42 Pages
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HT46R51/HT46R52
Bit No. Label
Function
0 ACS0
1 ACS1 Defines the analog channel select
2 ACS2
3
4
5
PCR0
PCR1
PCR2
Defines the port B configuration se-
lect. If PCR0, PCR1 and PCR2 are all
zero, the ADC circuit is powered off to
reduce power consumption
Indicates end of A/D conversion.
(0= end of A/D conversion)
Each time bits 3~5 change state the
A/D should be initialised by issuing a
6 EOCB START signal, otherwise the EOCB
flag may have an undefined condition.
See ²Important note for A/D initialis-
ation².
Starts the A/D conversion.
7
START
0®1®0= Start
0®1= Reset A/D
converter
and
set
EOCB to ²1².
ADCR (22H) Register
ACS2 ACS1 ACS0
Analog Channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
*
1
1
0
*
1
1
1
*
Analog Input Channel Selection
Note: * undefined, cannot be used
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADRL (20H) D3 D2 D1 D0 0 0 0 0
ADRH (21H) D11 D10 D9 D8 D7 D6 D5 D4
Note: D0~D11 is A/D conversion result data bit
LSB~MSB.
PCR2
PCR1
PCR0
4
3
2
1
0
0
0
0
PB4
PB3
PB2
PB1
PB0
0
0
1
PB4
PB3
PB2
PB1
AN0
0
1
0
PB4
PB3
PB2
AN1
AN0
0
1
1
PB4
PB3
AN2
AN1
AN0
1
0
0
PB4
AN3
AN2
AN1
AN0
1
0
1
AN4
AN3
AN2
AN1
AN0
1
1
0
1
1
1
Undefined, cannot be used
Port B Configuration
STAR T
M in im u m o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d
EO CB
A /D s a m p lin g tim e
tA D C S
A /D s a m p lin g tim e
tA D C S
A /D s a m p lin g tim e
tA D C S
P C R 2~
PCR0
000B
A C S 2~
ACS0
000B
P o w e r-o n
R eset
100B
010B
S ta rt o f A /D
c o n v e r s io n
100B
000B
S ta rt o f A /D
c o n v e r s io n
101B
001B
S ta rt o f A /D
c o n v e r s io n
000B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
d o n 't c a r e
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
E n d o f A /D
c o n v e r s io n
E n d o f A /D
c o n v e r s io n
E n d o f A /D
c o n v e r s io n
tA D C
tA D C
tA D C
A /D c o n v e r s io n tim e
A /D c o n v e r s io n tim e
A /D c o n v e r s io n tim e
N o te : A /D c lo c k m u s t b e fS Y S /2 , fS Y S /8 o r fS Y S /3 2
tA D C S = 3 2 tA D
tA D C = 8 0 tA D
A/D Conversion Timing
Rev. 1.40
17
July 12, 2005
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