HT46R53A データシートの表示（PDF） - Holtek Semiconductor

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HT46R53A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R53A/HT46R54A

Timer/Event Counter

Only one timer/event counter (TMR) are implemented in

the microcontroller. The timer/event counter contains an

8-bit programmable count-up counter and the clock may

come from an external source or an internal clock

source. An internal clock source comes from fSYS. The

external clock input allows the user to count external

events, measure time intervals or pulse widths, or to

generate an accurate time base.

There are two registers related to the Timer/event coun-

ter; TMR (0DH), TMRC (0EH). Writing TMR will transfer

the specified data to timer/event counter registers.

Reading the TMR will read the contents of the

timer/event counter. The TMRC is a control register,

which defines the operating mode, counting enable or

disable and an active edge.

The TM0 and TM1 bits define the operation mode. The

event count mode is used to count external events,

which means that the clock source is from an external

(TMR) pin. The timer mode functions as a normal timer

with the clock source coming from the internal selected

clock source. Finally, the pulse width measurement

mode can be used to count the high or low level duration

of the external signal (TMR), and the counting is based

on the internal selected clock source.

In the event count or timer mode, the timer/event coun-

ter starts counting at the current contents in the

timer/event counter and ends at FFH. Once an overflow

occurs, the counter is reloaded from the timer/event

counter preload register, and generates an interrupt re-

quest flag (TF; bit 5 of the INTC ). In the pulse width

measurement mode with the values of the TON and TE

bits equal to 1, after the TMR has received a transient

from low to high (or high to low if the TE bit is ²0²), it will

start counting until the TMR returns to the original level

and resets the TON. The measured result remains in the

timer/event counter even if the activated transient oc-

curs again. In other words, only 1-cycle measurement

can be made until the TON is set. The cycle measure-

ment will re-operate as long as it receives further tran-

sient pulse. In this operation mode, the timer/event

counter begins counting not according to the logic level

but to the transient edges. In the case of counter over-

flows, the counter is reloaded from the timer/event coun-

ter register and issues an interrupt request, as in the

other two modes, i.e., event and timer modes.

To enable the counting operation, the Timer ON bit

(TON; bit 4 of the TMRC) should be set to ²1². In the

pulse width measurement mode, the TON is automati-

cally cleared after the measurement cycle is completed.

But in the other two modes, the TON can only be reset

by instructions. The overflow of the timer/event counter

is one of the wake-up sources and can also be applied

to a PFD (Programmable Frequency Divider) output at

PA3 by options. No matter what the operation mode is,

writing a ²0² to ETI (bit2 of the INTC) disables the re-

lated interrupt service. When the PFD function is se-

lected, executing ²SET [PA].3² instruction to enable the

PFD output and executing ²CLR [PA].3² instruction to

disable the PFD output.

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register also re-

loads that data to the timer/event counter. But if the

timer/event counter is turn on, data written to the

timer/event counter is kept only in the timer/event coun-

ter preload register. The timer/event counter still contin-

ues its operation until an overflow occurs.

When the timer/event counter (TMR) is read, the clock is

blocked to avoid errors, as this may results in a counting

error. Blocking of the clock issue should be taken into

account by the programmer. It is strongly recommended

to load a desired value into the TMR register first, before

turning on the related timer/event counter, for proper op-

eration since the initial value of TMR is unknown. Due to

the timer/event scheme, the programmer should pay

special attention on the instruction to enable then dis-

able the timer for the first time, whenever there is a need

to use the timer/event function, to avoid unpredictable

result. After this procedure, the timer/event function can

be operated normally.

The bit0~bit2 of the TMRC can be used to define the

pre-scaling stages of the internal clock sources of the

timer/event counter. The definitions are as shown. The

overflow signal of the timer/event counter can be used

to generate the PFD signal. The timer prescaler is also

used as the PWM counter.

P r e lo a d R e g is te r

D a ta B u s

R e lo a d

P S C 2~P S C 0

fS Y S

8 - s ta g e p r e s c a le r

T M R in p u t

TE

TM 1 TM 0

T im e r /E v e n t C o u n te r

M o d e C o n tro l

TO N

T im e r /E v e n t

C o u n te r

8 - B it T im e r /E v e n t C o u n te r ¸ 2

O v e r flo w

to In te rru p t

PFD

8-Bit Timer/Event Counter Structure

Rev. 1.00

15

August 24, 2006

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