HT46R53A データシートの表示（PDF） - Holtek Semiconductor

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HT46R53A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R53A/HT46R54A

Each I/O line has its own control register (PAC, PBC,

PCC, PDC) to control the input/output configuration.

With this control register, CMOS output or Schmitt trig-

ger input with or without pull-high resistor structures can

be reconfigured dynamically under software control. To

function as an input, the corresponding latch of the con-

trol register must write ²1². The input source also de-

pends on the control register. If the control register bit is

²1², the input will read the pad state. If the control regis-

ter bit is ²0², the contents of the latches will move to the

internal bus. The latter is possible in the

²read-modify-write² instruction.

For output function, CMOS is the only configuration.

These control registers are mapped to locations 13H,

15H, 17H and 19H.

After a chip reset, these input/output lines remain at high

levels or floating state (dependent on pull-high options).

Each bit of these input/output latches can be set or

cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,

16H or 18H) instructions.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i², ²CLR

[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device. Each I/O port has a pull-high option. Once the

pull-high option is selected, the I/O port has a pull-high

resistor, otherwise, there¢s none. Take note that a non-

pull-high I/O port operating in input mode will cause a

floating state.

The PA3, PA4 and PA5 are pin-shared with PFD, TMR

and INT pins respectively.

If the PFD option is selected, the output signal in output

mode of PA3 will be the PFD signal generated by the

timer/event counter overflow signal. The input mode al-

ways remain in its original functions. Once the PFD op-

tion is selected, the PFD output signal is controlled by

the PA3 data register only. The I/O functions of PA3 are

shown below.

I/O

I/P

O/P

Mode (Normal) (Normal)

PA3

Logical

Input

Logical

Output

I/P

(PFD)

O/P

(PFD)

Logical

PFD

Input (Timer on)

Note: The PFD frequency is the timer/event counter

overflow frequency divided by 2.

The definitions of the PFD control signal and PFD output

frequency are listed in the following table.

Timer

Timer

Preload

Value

PA3 Data

Register

PA3 Pad

State

Frequency

OFF X

0

0

X

OFF X

1

U

X

ON

N

0

0

X

ON

N

1

PFD fINT/(2´(256-N))

Note:

²X² stands for ²unused²

²U² stands for ²unknown²

²N² is the preload value for the timer/event

counter

²fTMR² is the input clock frequency for the

timer/event counter

The PB can also be used as A/D converter inputs. The

A/D function will be described later. There is a PWM

function shared with PD0. If the PWM function is en-

abled, the PWM signal will appear on PD0 (if PD0 is op-

erating in output mode). The I/O functions of PD0 are as

shown.

I/O

Mode

PD0

I/P

O/P

(Normal) (Normal)

Logical Logical

Input Output

I/P

(PWM)

Logical

Input

O/P

(PWM)

PWM

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruction

to avoid consuming power under input floating state.

PWM

The microcontroller provides one channel PWM output

shared with PD0. The PWM supports (7+1) or (6+2)

modes which are selected by configuration option. The

PWM channel has their data register denoted as

PWM(1AH). The frequency source of the PWM counter

comes from fSYS. The PWM register is an 8-bit register.

The waveforms of the PWM outputs are as shown.

Once the PD0 are selected as the PWM outputs and the

output function of the PD0 are enabled (PDC.0= ²0²),

writing ²1² to PD0 data register will enable the PWM out-

put function and writing ²0² will force the PD0 to stay at

²0².

A (6+2) bits mode PWM cycle is divided into four modu-

lation cycles (modulation cycle 0~modulation cycle 3).

Each modulation cycle has 64 PWM input clock period.

In a (6+2) bit PWM function, the contents of the PWM

Rev. 1.00

17

August 24, 2006

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