HT46R63 データシートの表示（PDF） - Holtek Semiconductor

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HT46R63

(HT46R063B - HT46R065B) Enhanced A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R63/HT46C63

Once a wake-up event occurs, it takes 1024 tSYS (sys-

tem clock period) to resume normal operation. In other

words, a dummy period will be inserted after wake-up. If

the wake-up results from an interrupt acknowledgment,

the actual interrupt subroutine execution will be delayed

by one or more cycles. If the wake-up results in the next

instruction execution, this will be executed immediately

after the dummy period is finished.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

The 32.768kHz crystal oscillator still run or stop in the

halt mode. (decided by option)

Reset

There are three ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a ²warm re -

set² that resets only the PC and SP, leaving the other cir-

cuits in their original state. Some registers remain un-

changed during other reset conditions. Most registers

are reset to the ²initial condition² when the reset condi-

tions are met. By examining the PDF and TO flags, the

program can distinguish between different ²chip resets².

TO PDF

Reset Conditions

0 0 RES reset during power-up

u u RES reset during normal operation

0 1 RES wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² means unchanged

To guarantee that the system oscillator is started and

stabilized, the SST (system start-up timer) provides an

extra-delay to delay 1024 system clock pulses when

system power-up or the system awakes from the HALT

state.

When the system power-up occurs, the SST delay is

added during the reset period. But when the reset co-

mes from the RES pin, the SST delay is disabled. Any

wake-up from HALT will enable the SST delay.

An extra option load time delay is added during system

reset (power-up, WDT time-out at normal mode or RES

reset).

The chip reset statuses of the functional units are as

shown.

PC

000H

Interrupt

Disable

WDT

Clear. After master reset, WDT

begins counting

Timer/Event Counter Off

Input/Output Ports Input mode

SP

Points to the top of the stack

V DD

0 .0 1 m F *

100kW

RES

10kW

0 .1 m F *

Reset Circuit

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

H A LT

W DT

W a rm R e s e t

RES

O SC1

SST

1 0 - b it R ip p le

C o u n te r

C o ld

R eset

S y s te m R e s e t

Reset Configuration

VDD

RES

tS S T

S S T T im e - o u t

C h ip R e s e t

Reset Timing Chart

Rev. 1.90

15

May 17, 2004

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