HT46R63 データシートの表示（PDF） - Holtek Semiconductor

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HT46R63

(HT46R063B - HT46R065B) Enhanced A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R63/HT46C63

Timer/Event Counter

A timer/event counter is implemented in the device. The

timer/event counter contains a 16-bit programmable

count-up counter and the clock may come from an ex-

ternal source or the internal clock source.

The internal clock source is the system clock divided by

4: fSYS/4. The external clock input allows the user to

count external events, measure time intervals or pulse

widths, or to generate an accurate time base.

There are 3 registers related to timer/event counter;

TMRH(0CH), TMRL(0DH), TMRC(0EH). Writing TMRL

only stores the data into a low byte buffer, and writing

TMRH will put the written data and the low contents of

low byte buffer to preload register (16 bits) simulta-

neously. The timer/event counter preload register is

changed by writing TMRH operations and writing TMRL

will keep the timer/event counter preload register un-

changed.

Reading TMRH will also latch the TMRL into the low

byte buffer to avoid the false timing problem. Reading

TMRL returns the contents of the low byte buffer. In

other words, the low byte of timer/event counter cannot

be read directly. It has to read the TMRH first to make

the low byte contents of timer/event counter latched into

the buffer. The TMRC is the timer/event counter control

register, which defines the operating mode, counting en-

able or disable and active edge.

The TM0, TM1 bits define the operating mode. The

event count mode is used to count external events,

which means the clock source comes from an external

(TMR) pin. The timer mode functions as a normal timer

with the clock source coming from fSYS/4. The pulse

width measurement mode can be used to count the high

or low level duration of the external signal (TMR). The

counting is based on fSYS/4.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current

contents in the timer/event counter to FFFFH. Once

overflow occurs, the counter is reloaded from the

timer/event counter preload register and generates the

corresponding interrupt request flag (TF; bit 6 of INTC0)

at the same time.

In pulse width measurement mode with the TON and TE

bits are equal to one, once the TMR has received a tran-

sition from low to high (or high to low if the TE bit is 0) it

will start counting until the TMR returns to the original

level and reset the TON. The measured result will re-

main in the timer/event counter even if the activated

transition occurs again. In other words, only one cycle

measurement can be done. Until setting the TON, the

cycle measurement will function again as long as it re-

ceives further transition pulse. Note that, in this operat-

ing mode, the timer/event counter starts counting not

according to the logic level but according to the transi-

tion edges. In the case of counter overflows, the counter

is reloaded from the timer/event counter preload regis-

ter and issues the interrupt request just like the other two

modes.

To enable the counting operation, the timer ON bit (TON;

bit 4 of TMRC) should be set to 1. In the pulse width

measurement mode, the TON will be cleared automati-

cally after the measurement cycle is complete. But in the

other two modes the TON can only be reset by instruc-

tions. The overflow of the timer/event counter is one of

the wake-up sources. No matter what the operation

mode is, writing a 0 to ETI can disabled the correspond-

ing interrupt service.

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register will also

load the data to timer/event counter. But if the

timer/event counter is turned on, data written to the

timer/event counter will only be kept in the timer/event

counter preload register. The timer/event counter will

still operate until the overflow occurs (a timer/event

counter reloading will occur at the same time).

fS Y S /4

TM R

TM 1

TM 0

TE

1 6 - B it

T im e r /e v e n t C o u n te r

P r e lo a d R e g is te r

8 - B it

L o w B y te B u ffe r

R e lo a d

D a ta B u s

TM 1

TM 0

TO N

P u ls e W id th

M e a s u re m e n t

M o d e C o n tro l

1 6 - B it

T im e r /e v e n t C o u n te r

(T M R H , T M R L )

O v e r flo w to In te r r u p t

Timer/Event Counter

Rev. 1.90

17

May 17, 2004

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