HT46R65-52 データシートの表示（PDF） - Holtek Semiconductor
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HT46R65-52 Datasheet PDF : 48 Pages
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D a ta B u s
W r ite C o n tr o l R e g is te r
C h ip R e s e t
C o n tr o l B it
DQ
P u ll- h ig h
O p tio n
CK Q
S
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P A 0 /P A 1 /P A 3 /P D 0 /P D 1 /P D 2 /P D 3
B Z /B Z /P F D /P W M 0 /P W M 1 /P W M 2 /P W M 3
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly )
IN T 0 fo r P D 4 o n ly
IN T 1 fo r P D 5 o n ly
T M R 0 fo r P D 6 o n ly
T M R 1 fo r P D 7 o n ly
D a ta B it
DQ
CK Q
S
M
U
X
M
U
X
PFD EN
(P A 3 )
W a k e - u p O p tio n s
Input/Output Ports
HT46R65/HT46C65
V DD
P A 0 /B Z
P A 1 /B Z
PA2
P A 3 /P F D
P A 4~P A 7
P B 0 /A N 0 ~ P B 7 /A N 7
P D 0 /P W M 0
P D 1 /P W M 1
P D 2 /P W M 2
P D 3 /P W M 3
P D 4 /IN T 0
P D 5 /IN T 1
P D 6 /T M R 0
P D 7 /T M R 1
The PA0 and PA1 are pin-shared with BZ and BZ signal,
respectively. If the BZ/BZ option is selected, the output
signal in output mode of PA0/PA1 will be the buzzer sig-
nal generated by multi-function timer. The input mode
always remain in its original function. Once the BZ/BZ
option is selected, the buzzer output signal are con-
trolled by the PA0/PA1 data register only.
The I/O function of PA0/PA1 are shown below.
PA0 I/O
I I OOOOOOOO
PA1 I/O
I O I I I OOOOO
PA0 Mode
XXCBBCBBBB
PA1 Mode
XCXXXCCCBB
PA0 Data
PA1 Data
X X D 0 1 D0 0 1 0 1
X D X X X D1 D D X X
PA0 Pad Status I I D 0 B D0 0 B 0 B
PA1 Pad Status I D I I I D1 D D 0 B
Note:
²I² input; ²O² output
²D, D0, D1² Data
²B² buzzer option, BZ or BZ
²X² don¢t care
²C² CMOS output
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0/PD1/PD2/PD3. If the PWM
function is enabled, the PWM0/PWM1/PWM2/PWM3
signal will appear on PD0/PD1/PD2/PD3 (if PD0/PD1/
PD2/PD3 is operating in output mode). Writing ²1² to
PD0~PD3 data register will enable the PWM output
function and writing ²0² will force the PD0~PD3 to re-
main at ²0². The I/O functions of PD0/PD1/PD2/PD3 are
as shown.
I/O
I/P
O/P
Mode (Normal) (Normal)
PD0~ Logical Logical
PD3
Input Output
I/P
(PWM)
Logical
Input
O/P
(PWM)
PWM0~
PWM3
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
The definitions of PFD control signal and PFD output
frequency are listed in the following table.
Timer
Timer
Preload
Value
PA3 Data
Register
PA3 Pad
State
PFD
Frequency
OFF X
0
0
X
OFF X
1
U
X
ON
N
0
0
X
ON
N
1
PFD fTMR/[2´(M-N)]
Note:
²X² stands for unused
²U² stands for unknown
²M² is ²65536² for PFD0 or PFD1
²N² is preload value for timer/event counter
²fTMR² is input clock frequency for timer/event
counter
Rev. 1.80
20
July 14, 2005
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