HY27UF081G2M-T データシートの表示（PDF） - Hynix Semiconductor
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HY27UF081G2M-T Datasheet PDF : 48 Pages
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Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Parameter
1.8Volt
3.3Volt
Symbol
Unit
Min
Max Min
Max
CLE Setup time
CLE Hold time
CE# setup time
CE# hold time
WE# pulse width
ALE setup time
ALE hold time
Data setup time
Data hold time
Write Cycle time
WE# High hold time
ALE to Data Loading time
tCLS
5(2)
5(2)
ns
tCLH
15(2)
15(2)
ns
tCS
0
0
ns
tCH
10
10
ns
tWP
40(2)
40(2)
ns
tALS
5(2)
5(2)
ns
tALH
15(2)
15(2)
ns
tDS
25(2)
25(2)
ns
tDH
15
15
ns
tWC
60(2)
60(2)
ns
tWH
20
20
ns
tADL
100
100
ns
Data Transfer from Cell to register
ALE to RE# Delay (ID Read)
CLE to RE# Delay
tR
27(2)
27(2)
us
tAR
10
10
ns
tCLR
10
10
ns
Ready to RE# Low
RE# Pulse Width
WE# High to Busy
Read Cycle Time
RE# Access Time
RE# High to Output High Z
CE# High to Output High Z
RE or CE High to Output hold
tRR
20
20
ns
tRP
25(2)
25(2)
ns
tWB
100
100
ns
tRC
60(2)
60(2)
ns
tREA
30
30
ns
tRHZ
30
30
ns
tCHZ
20
20
ns
tOH
15
15
ns
RE# High Hold Time
Output High Z to RE# low
CE# Access Time
WE# High to RE# low
Device Resetting Time
(Read / Program / Erase)
tREH
tIR
tCEA
tWHR
tRST
30(2)
30(2)
ns
0
0
ns
45
45
ns
60
60
ns
5/10/500(1)
5/10/500(1)
us
Table 13: AC Timing Characteristics
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. These parameters are applied to the errata.
3. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
Rev 0.7 / Apr. 2005
21
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