HYS72D128300GBR-5-B データシートの表示（PDF） - Infineon Technologies
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HYS72D128300GBR-5-B Datasheet PDF : 45 Pages
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HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Electrical Characteristics
Table 12 AC Timing - Absolute Specifications –6/–5 (cont’d)
Parameter
Symbol
–5
DDR400B
–6
DDR333
Unit Note/ Test
Condition 1)
Min. Max. Min. Max.
Active to Precharge command
tRAS
40 70E+3 42 70E+3 ns 2)3)4)5)
Active to Active/Auto-refresh command
tRC
55 —
60 —
ns
2)3)4)5)
period
Auto-refresh to Active/Auto-refresh
command period
tRFC
65 —
72 —
ns
2)3)4)5)
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
tRCD
tRP
tRAP
tRRD
tWR
tDAL
tWTR
tXSNR
tXSRD
tREFI
15 —
18 —
ns
2)3)4)5)
15 —
18 —
ns
2)3)4)5)
15 —
18 —
ns
2)3)4)5)
10 —
12 —
ns
2)3)4)5)
15 —
15 —
ns
2)3)4)5)
(tWR/tCK) +
(tRP/tCK)
(tWR/tCK) + tCK 2)3)4)5)11)
(tRP/tCK)
1—
1—
tCK
2)3)4)5)
75 —
75 —
ns
2)3)4)5)
200 —
— 7.8
200 —
— 7.8
tCK
2)3)4)5)
µs
2)3)4)5)12)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VOH(ac) and VOL(ac).
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
21
Rev. 0.5, 2003-12
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