ICS85105I データシートの表示（PDF） - Integrated Device Technology
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ICS85105I
Integrated Device Technology
ICS85105I Datasheet PDF : 16 Pages
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ICS85105I
LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
GND
Power
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
2
CLK_EN Input Pullup When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVTTL / LVCMOS interface levels.
Clock select input. When HIGH, selects CLK1 input.
3
CLK_SEL Input Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVTTL / LVCMOS interface levels.
4
CLK0
Input Pulldown Non-inverting differential clock input.
5
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock input.
6
CLK1
Input Pulldown Single-ended clock input. LVTTL / LVCMOS interface levels.
7, 8
Q4, nQ4 Output
9
IREF
Input
Differential output pair. HCSL interface levels.
An external fixed precision resistor (475Ω) from this pin to ground provides
a reference current used for differential current-mode Qx/nQx outputs.
10, 13, 18
11, 12
VDD
nQ3, Q3
Power
Output
Positive supply pins.
Differential output pair. HCSL interface levels.
14, 15 nQ2, Q2 Output
Differential output pair. HCSL interface levels.
16, 17
nQ1, Q1 Output
Differential output pair. HCSL interface levels.
19, 20
nQ0, Q0 Output
Differential output pair. HCSL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT™ / ICS™ 0.7V HCSL FANOUT BUFFER
2
ICS85105AGI REV. A JUNE 5, 2008
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