IDT7009 データシートの表示（PDF） - Integrated Device Technology
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IDT7009 Datasheet PDF : 17 Pages
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IDT7009L
High-Speed 128K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
7009L15
Com'l Only
7009L20
Com'l Only
Symbol
Parameter
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
tBDA
BUSY Disable Time from Address Not Matched
tBAC
BUSY Acce ss Time from Chip Enable Low
tBDC
BUSY Acce ss Time from Chip Enable High
tAPS
Arbitration Priority Set-up Time(2)
tBDD
BUSY Disable to Valid Data(3)
tWH
Write Hold After BUSY(5)
BUSY TIMING (M/S=VIL)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
Min. Max. Min. Max. Unit
____
15
____
20
ns
____
15
____
20
ns
____
15
____
20
ns
____
15
____
17
ns
5
____
5
____
ns
____
15
____
17
ns
12
____
15
____
ns
0
____
0
____
ns
12
____
15
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
____
30
____
45
ns
____
25
____
30
ns
NOTES:
4839 tbl 14
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. Industrial Temperature: for specific speeds, packages and powers contact your sales office.
10
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