IDT7140SA100C データシートの表示（PDF） - Integrated Device Technology

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IDT7140SA100C

HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM

Integrated Device Technology 

IDT7130SA/LA and IDT7140SA/LA

High-Speed 1K x 8 Dual-Port Static SRAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)

ADDR"A"

R/W"A"

DATAIN"A"

ADDR"B"

BUSY"B"

DATAOUT"B"

tAPS(1)

tWC

MATCH

tWP

tDW

VALID

tBAA

MATCH

tBDA

tWDD

tDH

tBDD

tDDD

NOTES:

1. To ensure that the earlier of the two ports wins. tBDD is ignored for slave (IDT7140).

2. CEL = CER = VIL

3. OE = VIL for the reading port.

4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".

VALID

2689 drw 12

Timing Waveform of Write with BUSY(3)

tWP

R/W"A"

tWB

BUSY"B"

R/W"B"

tWH(1)

,

(2)

NOTES:

2689 drw 13

1. tWH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".

13

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