IDT7130SA100J データシートの表示（PDF） - Integrated Device Technology

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IDT7130SA100J

HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM

Integrated Device Technology 

IDT7130SA/LA and IDT7140SA/LA

High-Speed 1K x 8 Dual-Port Static SRAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical characteristics Over the

Operating Temperature and Supply Voltage Range(1)

7130X55

7140X55

Com'l, Ind

& Military

7130X100

7140X100

Com'l, Ind

& Military

Symbol

Parameter

Min. Max. Min. Max. Unit

INTERRUPT TIMING

tAS

Address Set-up Time

0

____

0

____

ns

tWR

Write Recovery Time

0

____

0

____

ns

tINS

Interrupt Set Time

____

45

____

60

ns

tINR

Interrupt Reset Time

____

45

____

60

ns

NOTES:

1. 'X' in part numbers indicates power rating (SA or LA).

2689 tbl 12b

Timing Waveform of Interrupt Mode(1)

INT Set:

ADDR'A'

tWC

INTERRUPT ADDRESS(2)

tAS(3)

tWR(4)

R/W'A'

INT'B'

tINS (3)

INT Clear:

ADDR'B'

OE'B'

INT'A'

tRC

INTERRUPT CLEAR ADDRESS

tAS(3)

tINR (3)

NOTES:.

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. See Interrupt Truth Table II.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

2689 drw 16

2689 drw 17

15

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