IDT71V35781SA200BGI データシートの表示（PDF） - Integrated Device Technology

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IDT71V35781SA200BGI

128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

Integrated Device Technology 

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)

Symbol

Parameter

Test Conditions

Min.

Max. Unit

|ILI|

Input Leakage Current

VDD = Max., VIN = 0V to VDD

___

5

µA

|ILZZ|

ZZ, LBO and JTAG Input Leakage Current(1)

VDD = Max., VIN = 0V to VDD

___

30

µA

|ILO|

Output Leakage Current

VOUT = 0V to VDDQ, Device Deselected

___

5

µA

VOL

Output Low Voltage

IOL = +8mA, VDD = Min.

___

0.4

V

VOH

Output High Voltage

IOH = -8mA, VDD = Min.

2.4

___

V

NOTE:

5301 tbl 08

1. The LBO, TMS, TDI, TCK & TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(1)

200MHz

183MHz

Symbol

Parameter

Test Conditions

Com'l Com'l

Ind

IDD Operating Power Supply

Current

Device Selected, Outputs Open, VDD = Max.,

VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2)

360

340

350

ISB1 CMOS Standby Power

Device Deselected, Outputs Open, VDD = Max.,

30

30

35

Supply Current

VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3)

ISB2 Clock Running Power

Supply Current

Device Deselected, Outputs Open, VDD = Max.,

VDDQ = Max., VIN > VHD or < VLD, f = fMAX(2,3)

130

120

130

IZZ Full Sleep Mode Supply

Current

ZZ > VHD, VDD = Max.

30

30

35

166 MHz

Com'l

Ind

320

330

30

35

110

120

30

35

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

Unit

mA

mA

mA

mA

5301 tbl 09

AC Test Conditions

(VDDQ = 3.3V)

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

AC Test Load

0 to 3V

2ns

1.5V

1.5V

See Figure 1

5301 tbl 10

I/O

6

5

4

∆tCD 3

(Typical, ns)

2

VDDQ/2

50Ω

Z0 = 50Ω

Figure 1. AC Test Load

, 5301 drw 06

1

20 30 50 80 100

Capacitance (pF)

, 200

5301 drw 07

Figure 2. Lumped Capacitive Load, Typical Derating

6.492

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